For Given machine instructions
LW R4 #400
L1:LW R1, 0,(R4)
LW R2 400(R4)
ADDI R3, R1, R2
SW R3, 0(R4)
SUB R4, R4, #4
BNZ R4, L1
on a 5 stage pipeline processor, 1 clock cycle per stage. how mAny clock cycles willtake execution of this segment on the regular architecture?