Self doubt

Question

Is there any general fromula for memory access time which include all the cases like cache hit, page fault, TLB hit etc.??

@arjun sir or anyone

Comments

Remember the hierarchy and you'll be fine - the TLB is a "cache" store virtual to physical address mappings. So any time an address conversion needs to be done, it'll be first checked in the TLB and if it's not present, it'll be checked in the main memory and the address is retrieved from there.

AFTER the address has been found, we'll first check the cache to see if the data corresponding to the address is present or not. If not, then we look into the main memory to find out the data from there. If it's still not there, the the page is fetched from the disk.

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just combining what @goxul said.

EMAT= (VA->PA) + (ACCESS THE WORD FROM THE MM)

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I think there is one previous gate question covering TLB and Cache