Pipeline

Question

please draw chart for this question

Answer 1

$10$ cycles are required.

Comments

@Weird_Boy use NPTEL lectures(one of those is delivered by Ajit Pal, IIT Kgp) to procure the following in pipeline:

1. RISC Pipeline
2. Pipeline Hazards
3. Ways to Reduce Stall cycles (i.e tackling hazards) --just introduction is required. In this operand forwarding is must; Do NOT go in-depth on topics like compiler rearrangements, tomasulo's algorithm.
4. Performance evaluation of a pipelined processor. 

It could be the case, we could have done that and that may be a latest update in technology too, But problem is that it is not discussed in NPTEL lectures(if found by anyone, please inform the GATEOverflow community about it), so we should avoid doing that by default.

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@Kapilp @vijaycs @habibkhan
Why there is stall at MA of first instruction  ?

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There is a stall  at MA of 1st instruction because the ADD operation is going to be done successfully only if we have the values of r2 and r0 .Here we have no issue with r2 since it is being used for the 1st time but for r0  it will be available only after the MA stage of load instruction.

So even though the operand forwarding mechanism is enabled , the operand buffer which is just after the MA stage is going to forward the value of r0 to the next cycle once the MA stage of load instruction is going to be completed.That is why we are not able to write  EX of add instruction directly under the MA of load instruction since the operand forwarding takes place by the buffer after the MA stage only.

In short , execute stage of ADD is only possible only if we get the value of r0 which we can get after MA stage of load instruction.So 1 stall is necessary.

Had there been no operand forwarding , then there would be 2 stalls instead of 1 since in that case execution is possible , as we know if we get the values of both r0 and r2 and r0 value will be obtained only after the WB(writeback) stage in that case.