Consider a $5$-stage instruction pipeline. The stages and the corresponding stage delays are given below.
| Instruction |
Stage delay |
| Fetch instruction (FI) |
3 ns |
| Decode instruction (DI) |
4 ns |
| Fetch operand (FO) |
7 ns |
| Execute instruction (EI) |
10 ns |
| Write result (WR) |
7 ns |
Assume that there is no delay between two consecutive stages. Consider a processor with a branch prediction mechanism by which it is always able to correctly predict the direction of the branch at the FI stage itself, without executing the branch instruction. A program consisting of a sequence of $10$ instructions $\mathrm{I} 1, \mathrm{I} 2, \ldots, \mathrm{I} 10$, is executed in the pipeline, where the $5^{\text {th}}$ instruction $\text{(I5)}$ is the only branch instruction and its branch target is the $8^{\text {th}}$ instruction $\text{(I8)}.$
- Draw the pipeline diagram over time showing how the instructions $\mathrm{I} 1, \mathrm{I} 2, \ldots, \mathrm{I} 10$ flow through the pipeline stages in this processor.
- Calculate the time (in ns) needed to execute the program.
