pc increment in cisc instructions

Question

When is incremented value of PC(program counter)  available in variable sized instructions?

during decode phase

after instruction execution

during fetch phase

none

Answer 1

During fetch phase, the PC is incremented by one. The incremented value is available after Fetch phase.

Comments

yes..then it is also available after instruction execution phase ....then what should be the answer...option a, b or d...

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I am not sure of the answer, but this is not a straight forward question.
Here we have a CISC processor, which has a variable sized instruction.
So, we may have to do multiple fetches.

Like if its a 2-word instruction.
1. Fetch word 1
2. Decode word 1
3. Fetch word 2
4. Decode word 2
5. Execute, etc.. . . .

So, i think the incremented value is available at Decode stage. It may not be available after instruction execution for multiple word instructions, after multiple fetches the previous incremented value of PC may be lost before the instruction completes. But I am not 100% sure if my reasoning is correct.

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I think you r right.. so finally i got the answer..thanks to you...