Consider a processor with an in-order five-stage pipeline (IF, ID, EX, MEM, and WB) with clock cycle time $10 \mathrm{~ns}$. This processor is executing a program in which $30 \%$ of the instructions are conditional branch instructions, $10 \%$ of the instructions are unconditional branch instructions. $40 \%$ of the conditional branches are taken. Branch target is available at the end of $2$nd stage for unconditional branches and at the end of $3$rd stage for conditional branches. Assume that the instruction following the branch is always started and ignored if the branch is taken. What is the throughput (Million instructions per second) of the system?
