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Consider a machine with a $2$-way set associative data cache of size $64$ Kbytes and block size $16$ bytes. The cache is managed using $32$ bit virtual addresses and the page size is $4$ Kbytes. A program to be run on this machine begins as follows:

double ARR[1024][1024];
int i, j;
/*Initialize array ARR to 0.0 */
for(i = 0; i < 1024; i++)
    for(j = 0; j < 1024; j++)
        ARR[i][j] = 0.0;


The size of double is $8$ bytes. Array $\text{ARR}$ is located in memory starting at the beginning of virtual page $\textsf{0xFF000}$ and stored in row major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by the program are those to array $\text{ARR}$.

The cache hit ratio for this initialization loop is:

  1. $0\%$
  2. $25\%$
  3. $50\%$
  4. $75\%$
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It brings 16 bytes(1 block = 16 bytes) at once, which is equal to 2 array elements(each element 8 bytes). Thus every alternate access will be a hit. 50%

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