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Recent questions tagged cache-memory

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GATE CSE 2026 | Set 2 | Question: Variation
Consider a system with 4 MB physical memory and a word length of 1 byte. The system uses a direct-mapped cache, with cache block numbers starting from 0. The word with ph...
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Cache Memory
$\begin{array}{l}\textbf{Q. } \text{A processor has the cache hierarchy as given. Assume that 20\% of instructions are}\\\text{load/store instructions. The remaining 80\%...
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Victim Cache Memory
Assume 15% of L1 misses are resolved in the victim cache. If retrieving data from the victim cache takes 4 cycles and retrieving data from main memory take 50 cycles, by ...
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Cache Memory CPI Question (Some US University)
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COA
A computer's memory hierarchy has a single cache with a 8.5ns access time and a 98% hit rate. Main memory has a 100 ns access time. If we replace the cache with another o...
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COA
Consider a write through cache which can fulfil 76.5% of CPU’s all memory requirements. Main memory has an access time of 1000ns, cache memory access time is 100ns. Cache...
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GATE CSE 2026 | Set 2 | Question: 42
Consider a system with a processor and a $4$ KB direct mapped cache with block size of $16$ bytes. The system has a $16$ MB physical memory. Four words $\mathrm{P}, \math...
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GATE CSE 2026 | Set 2 | Question: 46
Consider a system with $1$ MB physical memory and a word length of $1$ byte. The system uses a direct mapped cache, with block numbers starting from $0$. The word with ph...
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GATE CSE 2026 | Set 1 | Question: 28
The size of the physical address space of a processor is $2^{32}$ bytes. The capacity of a cache memory unit is $2^{23}$ bytes. The cache block size is $128$ bytes. The c...
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GATE CSE 2026 | Set 1 | Question: 44
Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation ...
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GATE CSE 2026 | Set 1 | COA | Memory Based | Question 48
Consider a system with the following cache configuration:Block size $=128$ bytes Physical memory size $=2^{23}$ bytes Cache size $=2^{13}$ bytes Two cache organization...
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Cache mapping
 
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Practice Type | COA | Memory Mapping |
Tag field size is ‘x’ bits in a 2 way block set associative mapped cache memory. The tag field size (in bits) when the system is upgraded to 8 way block set associative m...
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Write Through Cache Question
Consider a two-level memory organization. L1 (cache) has an access time of 10 ns and the main memory has an access time of 100 ns. Assume that the hit ratio for read oper...
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Interesting Question on Cache Memory, CPI
A processor has a base CPI of 1.2. Every instruction requires one instruction fetch, and 30% of instructions are loads and 10% are stores.The L1 cache miss rate (same for...
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GATE CS Practice : The "Dirty Bit" Avalanche (COA)
A system has a 2-level cache (L1, L2) and Main memory.L1 Hit Time: 1 nsL2 Hit Time: 10 nsMain Memory Access Time: 100 nsL1 Hit Rate: 90%L2 Hit Rate: (Global) 95% (Wait! I...
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Test ques.
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