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I/O devices operate asynchronously. So there should be some mechanism for the device to inform the CPU that it is ready to send or accept data. Here, the R flag does the trick. If interrupts are enabled (Interrupt Enable flag is set to 1 i.e., IEN=1), then whenever either input flag (FGI) or output flag (FGO) goes to 1, the R flag also gets set. (R = FGI "OR" FGO) This allows the system to easily check whether any I/O device needs service. If R = 0, the CPU goes through a normal instruction cycle. If R = 1, the CPU branches to the ISR to process an I/O transaction.
For a normal instruction cycle, everthing that happens during an instruction fetch and decode cycle are controlled by timing variables $T_0$, $T_1$ and $T_2$. The following things happen:
$T_0$: Address of the next instruction available in program counter PC is transferred to memory address register MAR.
$T_1$: Contents of MAR is fetched to the instruction register IR.
$T_2$: Instruction is decoded to the data lines $D_{0-7}$ and address loaded to MAR. Somewhere in between $T_1$ and $T_2$, PC is incremented.
R will be set whenever neither $T_0$, $T_1$ or $T_2$ is set, i.e., NOR of $T_0$, $T_1$ and $T_2$. The set input J of the flip flop is fed with ($T_0$ + $T_1$ + $T_2$)' "AND" IEN "AND" (FGI "OR" FGO) to get R=1.
