It should depend on when both requests come. Since DMA access bus by cycle stealing(or between cycles) and interrupts are checked before fetching a new instruction, DMA has an upper hand here. Also DMA requires only bus and not CPU, whereas an interrupt may require both. So in case an instruction is being executed, DMA will get its bus first. In case: "before fetching a new instruction", anyone's request could get satisfied first. Plus, this case might also depend on implementation of the microprocessor.