Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 21

Question

In a computer system, there are $5$ registers, namely -- $PC, AR, DR, IR,$ and $SC$. The initial content of $PC$ is $7FF$. The content of memory at address $7FF$ is $EA9F$;  at address $A9F$ is $0C35$;  at address $C35$ is $FFFF$. (All register contents are in hexadecimal format).

When an ISZ indirect instruction is fetched from memory and executed, the content of $PC$ register after $6$ clock pulse is ________ (put the integer value of register content).

Answer 1

T0:AR<-PC Ar<-7FF

T1:IR<-M[AR];PC<-PC+1 IR<-EA9F and PC<-800

T2:Decode and AR<-IR(0....11) AR<-A9F

T3:AR<-M[AR] AR<-0C35

these 4 cycles will be common to all instructions ie Fetch,decode and compute effective address

Now for execute phase:

T4:DR<-M[AR] DR<FFFF

T5:DR<-DR+1 DR<-0000

T6:M[AR]<-DR;if (DR==0) then PC<-PC+1; SC<-0.....condition is true therefore PC<-801

Answer 2

Timing signals	PC Register content	AR	DR	IR	SC
Initial	7FF				0
T0	7FF	7FF			1
T1	800	7FF		EA9F	2
T2	800	A9F		EA9F	3
T3	800	C35		EA9F	4
T4	800	C35	FFFF	EA9F	5
T5	800	C35	0000	EA9F	6
T6	801	C35	0000	EA9F	0

 
 

Comments

 ISZ indirect instruction

http://homepage.divms.uiowa.edu/~jones/pdp8/man/mri.html#isz

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Sir, didnt get what is happening here.Please explain.Why no increment from t2 to t5?

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plz check the diagram..

The initial content of PC is 7FF.

The content of memory at address 7FF is EA9F, it store in IR register after 1st clock pulse.

In 2nd clock pulse AR is store with memory address A9F.

 The content of memory at address A9F is C35, it goes to store in AR at 3rd clock pulse.

In 4th clock pulse DR register is updated with  FFFF.

In 5th clock pulse DR value increase by 1 and goes to 0000 from FFFF

During these 5 clock pulses (T1 to T5) PC value remain same ,  then PC value increase by 1 due to Indirect instruction, PC = PC+1; previous PC value 800 new value become 801.