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UGC NET CSE | December 2025 | Part 2 | Question: 97
A system transfer data blocks of $2000$ bytes with programmed I/O, each byte transfer takes $6$ CPU cycles, with direct memory access (DMA), the block transfer takes $300...
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UGC NET CSE | December 2025 | Part 2 | Question: 100
A system transfer data blocks of $2000$ bytes with programmed I/O, each byte transfer takes $6$ CPU cycles, with direct memory access (DMA), the block transfer takes $300...
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Practice Type | COA | DMA Controller |
A DMA controller is used to make data transfer in burst mode. To transfer the data size of 780 KB (1 KB = 1024 Bytes); minimum number of bus grant signals that can be iss...
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#Gate , #COA, #DMA_transfer ,#modes_of_data_transfer
<! StartFragment >A device is constantly transferring the data with 20KBps speed to memory using DMA. Assume that the transmission time to memory from IO once the data (...
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COA , IO DMA tranfer
During DMA transfers, the CPU is momentarily halted while the DMA controller takes control of the system busTrue or False?
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UGC NET CSE | August 2024 | Part 2 | Question: 43
Arrange the given steps required for a Direct Memory Access (DMA) transfer in the correct order.Initiate DMA transfer requestTransfer data directly between peripheral and...
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UGC NET CSE | December 2023 | Part 2 | Question: 44
The interface(s) that provide(s) I/O transfer of data directly to and from the memory unit peripheral is/are termed as :DMA (Direct Memory Access)IOP (Input-Output Proces...
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DMA | CPU AND DMA overlap | made easy test series full length basic 1
is'nt it possible for CPU And DMA cycles to overlapp if cpu does some cpu intensive work which does not need Bus
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DMA
Consider 4 MBPS IO devices connected to 64 bit CPU using DMA interface. 64 words data is transfer from the IO to memory using DMA interface. Main memory machine cycle tim...
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DMA
Consider a disk with data transfer rate 50MBPS. It is operated with cycle stealing mode of DMA. Here whenever 64bits information is available it is transferred in 40ns. W...
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GATE CSE 2024 | Set 2 | Question: 1
​​​Consider a computer with a $4 \mathrm{MHz}$ processor. Its $\text{DMA}$ controller can transfer $8$ bytes in $1$ cycle from a device to main memory through cycle steal...
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GATE CSE 2024 | Set 1 | Question: 5
​​​​Which one of the following statements is FALSE?In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cy...
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COA - DMA
A hard disk with a transfer rate of 1 Mbytes/ second is constantly transferring data to memory using DMA. The processor runs at 500 MHz, and takes 500 and 1000 clock cycl...
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Gate
An I/O device transfers data at a rate of 10MB/s over a 100MB/S bus. The data is transferred in 4KB blocks. If the processor operates at 500MHz, and it takes a total of 5...
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I/O Modes | Process State Transition | COA & OS
MSQA ‘Running’ process is surely put into ‘Blocked/Wait’ state during while requesting for an I/O, in which of the following I/O modes?Synchronous I/OAsynchronous I/OInte...
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DMA
The below question is from Made Easy Test seriesThe diagram shows single bus detached DMA configuration for a system. How many times system bus is used for single data tr...
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University Assignment
Question → Consider a system in which bus cycles take 500 ns. Transfer of bus control in either direction, from processor to I/O device or vice-versa, takes 250 ns. One o...
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GATE CSE 2022 | Question: 7
Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?$\text{DMA}$ based $\text{I/O}$ transferInterrupt d...
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GATE CSE 2021 | Set 2 | Question: 20
Consider a computer system with $\text{DMA}$ support. The $\text{DMA}$ module is transferring one $8$-bit character in one $\text{CPU}$ cycle from a device to memory thro...
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Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 7 (Page No. 430)
One mode that some DMA controllers use is to have the device controller send the word to the DMA controller, which then issues a second bus request to write to memory. Ho...
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Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 6 (Page No. 429 - 430)
Suppose that a system uses DMA for data transfer from disk controller to main memory. Further assume that it takes $t_{1}\: nsec$ on average to acquire the bus and $t_{2}...
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Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 5 (Page No. 429)
A DMA controller has five channels. The controller is capable of requesting a $32$-bit word every $40\: nsec.$ A response takes equally long. How fast does the bus have t...
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