Recent questions tagged machine-instruction

Consider a processor that has $16$ general purpose registers and it uses $2$-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There...

Consider a 16 bit hypothetical processor which support 1 word long instruction. Processor has 30 registers and 4KB of memory size. If there exists '11' 2 address register...

2.A byte addressable computer has a memory capacity of 2^m KB( kbytes ) and can perform 2^n operations. What will be the size of an instruction involving 3 operands and o...

Consider two machines M1 and M2. For both machines, all instructions except for mispredicted branches take one cycle. Mispredicted branches take one cycle plus an additio...

Which of the following are not data manipulation instructions?CallLoudAndIncrementShiftChoose the correct answer from the options given below:$\text{III $\&$ V only}$$\te...

Which of the following do not represent memory reference instruction.$\begin{array}{|c|c|c|} \hline 1 & \text{opcode} & \\ \hline \end{array}$ mode $=1$, opcode $=010$$\b...

A processor has $64$ general-purpose registers and $50$ distinct instruction types. An instruction is encoded in $32$-bits. What is the maximum number of bits that can be...

Consider a hypothetical CPU that supports the following instruction set:- $\text{ADD } R_i, R_j$ - $\text{SUB } R_i, R_j$ - $\text{MOV } R_i, R_j$ - $\text{AND } R_i, ...

How I2-I4 is counted?

I have seen lots of questions like this :A load-store architecture in which memory operation applied only on LOAD and STORE instructions and other all operations are REG-...

A CPU has instructions 12 bits long. The size of an address field is 4 bits. It is possible to have: 14 commands of two addresses 29 commands of an address 48 zero-addres...

Machine Level Language is a/anAssembly LanguageLow Level languageHigh level LanguageTranslating Language 

Consider the given $\text{C}$-code and its corresponding assembly code, with a few operands $\text{U1-U4}$ being unknown. Some useful information as well as the semantics...

Consider a 4 way set associative cache of size 16 KB organized into 4 words block. Cache memory is designed with the write back protocol having the miss ratio of read and...

Consider a system that supports 2-address, 1-address, and 0-address instructions. The system has 'i' bits instructions and 'a' bits addresses. If there are 'x' 2-address ...

MSQWhich among the following statements is/are TRUE for a pipelined RISC computer.PC is usually incremented during Instruction Cycle (IF,ID)PC may be incremented during ...

During the instruction fetch does the program counter increment in the same clock cycle or it take next clock cycle