Recent activity by Sanjiv Kumar / GATE Overflow for GATE CSE

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1

GATE CSE 2023 | Question: 3
Let $\textsf{SLLdel}$ be a function that deletes a node in a singly-linked list given a pointer to the node and a pointer to the head of the list. Similarly, let $\textsf{DLLdel}$ be another function that deletes a node in a doubly-linked list given a pointer to the node ... $\textsf{DLLdel}$ are $O(1)$ $\textsf{SLLdel}$ is $O(n)$ and $\textsf{DLLdel}$ is $O(1)$

Let $\textsf{SLLdel}$ be a function that deletes a node in a singly-linked list given a pointer to the node and a pointer to the head of the list. Similarly, let $\textsf...

10.9k views

answered Aug 27, 2023

3 answers

2

GATE CSE 2008 | Question: 18
Which combination of the integer variables $x, y,$ and $z$ makes the variable $a$ get the value $4$ in the following expression? $a=(x > y)?((x > z) ?x:z): ((y > z) ?y:z)$ $x=3, y=4, z=2$ $x=6, y=5, z=3$ $x=6, y=3, z=5$ $x=5, y=4, z=5$

Which combination of the integer variables $x, y,$ and $z$ makes the variable $a$ get the value $4$ in the following expression?$$a=(x y)?((x z) ?x:z): ((y z) ?y:z)$$$...

12.7k views

answered Aug 10, 2023

5 answers

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GATE IT 2006 | Question: 79
A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX ... is used. The number of clock cycles required to complete the sequence of instructions is $10$ $12$ $14$ $16$

A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The...

17.8k views

answered Aug 7, 2023

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