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Answers by anurag_yo
1
votes
1
GATE CSE 2006 | Question: 42
A CPU has a five-stage pipeline and runs at $1$ GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new ... : $\text{1.0 second}$ $\text{1.2 seconds}$ $\text{1.4 seconds}$ $\text{1.6 seconds}$
A CPU has a five-stage pipeline and runs at $1$ GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the...
21.7k
views
answered
Dec 21, 2020
CO and Architecture
gatecse-2006
co-and-architecture
pipelining
normal
+
–
3
votes
2
GATE CSE 2003 | Question: 58
Consider the translation scheme shown below. $S \rightarrow T\;R$ $R \rightarrow + T \{\text{print}( +');\} R\mid \varepsilon$ $T \rightarrow$ num $\{\text{print}$(num.val)$;\}$ Here num is a token that represents an integer and num.val represents the corresponding integer value. For an ... scheme will print $9 + 5 + 2$ $9 \ 5 + 2 +$ $9 \ 5 \ 2 + +$ $+ + 9 \ 5 \ 2$
Consider the translation scheme shown below.$S \rightarrow T\;R$$R \rightarrow + T \{\text{print}(‘+’);\} R\mid \varepsilon$$T \rightarrow$ num $\{\text{print}$(num....
13.0k
views
answered
Aug 6, 2020
Compiler Design
gatecse-2003
compiler-design
grammar
normal
+
–
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