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Recent questions tagged cache-memory

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GATE CSE 2024 | Set 1 | Question: 43
Consider two set-associative cache memory architectures: $\text{WBC}$, which uses the write back policy, and $\text{WTC}$, which uses the write ... the victim cache block to main memory before loading the missed block to the cache
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GATE CSE 2024 | Set 1 | Question: 46
A given program has $25 \%$ load/store instructions. Suppose the ideal $\text{CPI}$ (cycles per instruction) without any memory stalls is $2$. The program ... a perfect cache (i.e., with NO data or instruction cache misses) is __________.
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GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 55
Consider the cache of size 512 bytes that is direct-mapped?Suppose the size of integer is 4 bytes and block size is 16 bytes. Assume cache is initially empty ... }What is the miss rate for the above loop? (roundoff to two decimal places)
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GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 54
Assume a cache memory with the following properties:The cache size $\text{(C)}$ is 512 bytes (contains $512$ data bytes)The cache uses an LRU (least recently used) policy ... $\text{B}=8$ bytes$\text{B}=16$ bytesNone of the above.
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GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 5
Suppose we have a four-way set associative physically addressed cache of size $256 \mathrm{KB}$ and $\text{16B}$ blocks, on a machine that uses $32$-bit physical addresses. How many bits will be used for the index?
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GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 50
A computer has a $32$-bit address bus with a direct mapped cache, using $4$ bits for block offset, $16$ tag bits, and $12$ index bits.Which of the following address ... $\textsf{2233 445 5}$ and $\textsf{2233 445 C}$
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GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 34
Which of the following is the best justification for using the middle bits of an address as the set index into a cache rather than the most significant ... efficient use of the cache with middle-bit indexing than with high-bit indexing.
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Made Easy Test Series 2024
Can anyone please confirm that below statement is correct or not : -Statement 3 is false for Only Full Associative cache mapping and for direct and set ... of this concept(Answer)https://gateoverflow.in/409971/made-easy-test-series-2024
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Hit Latency | Computer Organization
is this formula is correct if it is correct then in gate 2006 Question 75 why they not used this formulahttps://gateoverflow.in/43565/gate-cse-2006-question-75
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Computer Organisation Textbook Questions
Consider the case memory which has 0.8 and 0.9 hit ratio for read and write operation. Whenever there exist here miss either read or write 2 ... find average access time for write operation,3. average access time overall and throughput.
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