Test by Bikram | Mock GATE | Test 4 | Question: 51

Question

In a synchronous series counter of Modulus $256$, the propagation delay for each $2$ input AND gate is $5$ ns and for each flip-flop is $25$ ns. The maximum frequency of the Mod-256 counter is _____MHz.

Comments

In synchronous counters, the same clock is applied to all instances of flip flops.

Propagation delay for AND gate (combinational circuit ) = $5$ $ns$

Propagation delay for flip flop $=$ $25 ns$

Our cycle time should be at least big enough so that output from one flip flop and the combinational circuit should radiate to next flip flop input so that for next clock cycle this flip flop will active.

Time(of $1$ cycle) >= Time taken by flip flop + time taken by combinational circuit

                       $T  > = 25 ns +  5 ns$

                      $ T >= 30 ns$

 time period = $1 / frequency$

                      $1/F >= 30 ns$

                         $F<= 33.33 Mhz$

Plz, correct me where I m doing mistake???

@Bikram Sir

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with one single gate you cannot count till 256 .

http://www.allaboutcircuits.com/textbook/digital/chpt-11/synchronous-counters/

Answer 1

maximum frequency for synchronous series counter
= 1/ flip-flop delay + (n-2) AND gate delay  [ n = 8 as 256 = 2^8 ]
= 1/ 25+6*5
=18.18 Mhz

Comments

@Bikram sir,

how r u doing (n-2 ) AND gate delays???

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how r u doing (n-2 ) AND gate delays???

According to question. for MOD-256 counter we need 8 flip-flops

so we need (8-2) AND gates in series connection (as mentioned two input AND gates only)

n= number of flip flops and 2= number of 2 input AND gates.

Here propagation delay of FF  is taken  and also in question given that  2 - input AND gate , so here if we design that in initial first two FF doesn't required any AND gate but AND gate is required from third FF because it takes a 2-input FF from FF1 and FF2  so that here initial FF1 and FF2 not required any FF other than all FF required FF so here total   (n-FF) so we need to subtract two FF.   so its final (n-2) AND Gate delays .

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@Bikram sir

If we check ,

J₃=Q₂Q₁Q₀ ----> = (Output from AND gate1) . Q₂ ---------> We here effectively needs only 1 AND gate Delay

K₃=Q₂Q₁Q₀

//Output from AND gate1 = Q₁Q₀

Similarly ,

J₇=Q₆Q₅Q₄Q₃ Q₂Q₁Q₀ ----> = (Output from AND gate6) . Q₆ ---------> We here effectively needs only 1 AND gate Delay

K₇=Q₆Q₅Q₄Q₃ Q₂Q₁Q₀

//Output from AND gate6 = Q₅Q₄Q₃ Q₂Q₁Q₀

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As akash.dinkar12 above commented,

In synchronous counters, the same clock is applied to all instances of flip flops.

Propagation delay for AND gate (combinational circuit ) = 5 ns

Propagation delay for flip flop = 25ns

Our cycle time should be at least big enough so that output from one flip flop and the combinational circuit should radiate to next flip flop input so that for next clock cycle this flip flop will active.

Time(of 1 cycle) >= Time taken by flip flop + time taken by combinational circuit

                       T>=25ns+5ns

                      T>=30ns

 time period = 1/frequency

                      1/F>=30ns

                         F<=33.33Mhz
@akash.dinkar12

Can you verify?

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i also got 33.33MHz i m not getting solution can @Shaik Masthan @Magma @Mk Utkarsh plz explain

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For series synchronous counter :-

T$_{CLK}$ ≥ T$_{FF}$ + (n-2)T$_{AND}$

 

For parallel synchronous counter :-

T$_{CLK}$ ≥ T$_{FF}$ + T$_{AND}$

Now you will get the answer !

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in place of Tand there may be any Combinational circuit?

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yes, you can have any combinational circuit !

if it is replaced with any combinational circuit, then it is not standard series synchronous counter !

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@Shaik Masthan @akash.dinkar12 why even we need AND gates, with 8 flip flops we can make mod 256 counter, hence the answer should be $1/25 ns= 40mhz$. Am i missing something?

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that is standard series synchronous counter, !

can you make a synchronous counter with 8 FF's which produce mod-256 ? i don't know how to make it !

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@Shaik Masthan yes, we can't make a synchronous binary counter without the help of AND gate for more than 2 flip flops.

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if it is replaced with any combinational circuit, then it is not standard series synchronous counter !

 this statement means--> it is not a series synchronous counter

or it is a series synchronous counter