Consider the following Program segment for a CPU having three Registers $R1 ,R2 ,R3$.
$\begin{array}{|l|l|l|} \hline \text{Instruction} & \text{Operation} & \text{Instruction} \\ {} & {} & \text{Size In Words} \\ \hline \text{MOV } R1, 500 & R1 \leftarrow [500] & 2 \\ \hline \text{MUL } R3, R1 & R3 \leftarrow R3 ^* R1 & 1 \\ \hline \text{ADD } R2, R1 & R2 \leftarrow R2+R1 & 1 \\ \hline \text{MOV } 500, R3 & m[500] \leftarrow R3 & 2 \\ \hline \text{HALT} & \text{Machine Halts} & 1 \\ \hline \end{array}$
Consider that the memory is byte addressable with word size $16$ bits and the program has been loaded starting from memory location $500$. If an interrupt occurs while the Add instruction is getting executing by the CPU, then the return address saved onto the stack will be _________