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Given

Page table entry size = address translation bits + a valid bit + a modified bit + 2 replacement bits

page size = 16KB

physical address = 32 bits

#f frames = 2^32 /2^14 = 2^18

Page table entry size = 18+1+1+2 =22bits

page table size = 22MB

#f pages = page table size / Page table entry size

= 22* 2^20 * 8 bits / 22 bits

= 2^23

logical address = #f bits required to represent pages + offset

= 23+14 =37bits

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yes 37 is correct one

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3lurryface asked Jan 9, 2019
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If there is 2 or more level paging for processes, is it possible to have more than 1 page fault while accessing any single addressable unit(byte or word) ?