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Consider a system with cycles per instruction (CPI) is 1.0 when all memory accesses hit in the cache. The only data accesses are loads and stores, and these are 50% of the total instructions. If the miss penalty is 30 clock cycles and the miss rate is 4%, how much faster would the computer be if all instructions were cache hits?

(A) 1

(B) 2.8

(C) 1.6

(D) 3.5

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ANS : b 2.8

CPU execution time considering all cache access are hits

(CPUExTimeWithAllHits) = IC(Instruction count) * (CPU clock cycles + memory stall cycles) * clock cycle time

= IC ( 1+ 0) * clock cycle time

= IC * clock cycle time

CPU execution time considering misses in cache

(CPUExTimeWithMissRate) = IC(Instruction count) * (CPU clock cycles + memory stall cycles) * clock cycle time
memory stall cycles(Stall Cycles Per Instruction) = (Memory accesses per instr) * miss rate * miss penalty
Memory accesses per instruction = 1 + 0.5 (1 instruction access + 0.5 data access)
memory stall cycles Per Instruction = 1.5 * 0.04 * 30 = 1.8

= IC ( 1 + 1.8) * clock cycle time

= IC * 2.8 * clock cycle time

 

The performance ratio = (CPUExTimeWithMissRate/ CPUExTimeWithAllHits)

= (IC * 2.8 * clock cycle time ) / IC * clock cycle time

= 2.8

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