Consider a system with cycles per instruction (CPI) is 1.0 when all memory accesses hit in the cache. The only data accesses are loads and stores, and these are 50% of the total instructions. If the miss penalty is 30 clock cycles and the miss rate is 4%, how much faster would the computer be if all instructions were cache hits?
(A) 1
(B) 2.8
(C) 1.6
(D) 3.5