Test series

Question

Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 17 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 100 instructions I1, I2, I3, …, I100 is executed in this pipelined processor. Instruction I17 is the only branch instruction and its branch target is I91. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is ________ .
(A) 612
(B) 1854
(C) 1133
(D) 578

Comments

is option A correct..?

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option A is correct

Answer 1

answer will be A

Answer 2

It should be 612. A
I1 to I16   18*5 + 18*15 +
I91 to I100 18*5 + 18*9
i think previously it is 1000 instruction.

Comments

612 ns(34 clocks) is correct.

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@ Arpit Dhuriya

first thing...total number of instruction for given question is ....100 not 1000

second thing...you have consider from I1 to I16 you have consider CPU as non_pipiline.

...till 1- 16 it will taken 16Clock..after then..I17 will take..4clock to decide(as branch isnot predictable)..then 91th istruction will take 5clock and then remaining 9 instruction will take 1 clock/ints ...

total clock neede is...16+4+5+9=34..34*18=612