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On a non-pipelined sequential processor, a program segment, which is the part of the interrupt service routine, is given to transfer $500$ bytes from an I/O device to memory.

        Initialize the address register
        Initialize the count to 500
LOOP:   Load a byte from device              
        Store in memory at address given by address register
        Increment the address register
        Decrement the count
        If count !=0 go to LOOP

Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute.

The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires $20$ clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.

What is the approximate speed up when the DMA controller based design is used in a place of the interrupt driven program based input-output?

  1. $3.4$
  2. $4.4$
  3. $5.1$
  4. $6.7$

4 Answers

Best answer
129 129 votes
$$\begin{array}{llc} & \textbf{Statement} & \textbf{Clock Cycles(s) Needed} \\\hline
& \text{Initialize the address register} & \text{1} \\
& \text{Initialize the count to 500} & \text{1} \\
\text{LOOP:} &\textbf{Load}\text{ a byte from device} & \text{2}  \\
& \textbf{Store}\text{ in memory at address given by address register} & \text{2} \\
& \text{Increment the address register} & \text{1} \\ & \text{Decrement the count} & \text{1} \\
& \text{If count != 0 go to LOOP} & \text{1}  \end{array}$$
Interrupt driven transfer time $= 1+1+500\times(2+2+1+1+1) = 3502$

DMA based transfer time $= 20+500\times 2 = 1020$

Speedup $= 3502/1020 = 3.4$

Correct Answer: $A$
• edited by
3 3 votes
It is a good question ,i am here to help you understand it clearly .

so the first step is what the question is asking and what it has given us.
There is a non piplelined processor and some data transfer is going on between i/0 memory .
the question has mentioned about two ways in which data transfer is happenning one way is through Cpu helping them
and in other Dma is there for data transfer .

The question has asked us about how speed up which is nothing more than
=== Time required to do data transfer when Cpu is invilved (Interrupt service ) /   Time required to do data transfer when Dma is involed

Task 1==Calculate time required when Interrupt is there or you can say when Cpu is there
for this given information are
Every instruction is taking 1 clock Cycle  except load and  store they are taking 2 clock cycle
We need to transfer 500 B of data.
SO Time in task is all about time required in The code of instruction given

Initialize the address register-->t1
Initialize the count to 500------>t2
LOOP: Load a byte from device--->t3
 Store in memory at address given by address register-->t4
Increment the address register--->t5

 Decrement the count---->t6
If count !=0 go to LOOP----->t7

so t1 ,t2 will require only one one clock cycle each as they are simple instruction and they have mentioned about this .
and instruction from line t3-t7 wiill require how much time ,there are 500B of data to transfer and
if watch the loop carefullly then you will see how it is working it is working for count =500 because we need to transfer 500 B of data at all.

no so total clock cycle required =500(2+2+1+1+1)=3500clock cycle (Beacause 2- load ,2-store and 1 for remaining type of instruction)

so now total time or total clcok cycle required =1+1+3500=3502 clock cycle ---------------->>>>R1

Task 2 : Time required in Dma transfer
so in Dma what happens is we don't require CPu for data transfer ,so don't need to run the code as because cod eis for interrpt service routine and we don't to run it as because we are using Dma .

so its given that   :::  The DMA controller requires clock cycles for initialization and other overheads
and one more thing given ::::: Each DMA transfer
cycle takes two clock cycles to transfer one byte of data from the device to the memory

so time required usnig Dma controller=20 + 500 * 2=1020 Clock cycles.-------------->R2

so  final step ,result or speed up= R1/R2
                                                      =3402/1020
                                                      =3.4(ANS)
0 0 votes

Why we use a loop: In the interrupt method, the CPU is forced to pick up one byte, save one byte, update the address, and check the count. It can only process data byte-by-byte

Why we multiply by 500: Because the code inside the loop only handles 1 byte , and the program forces the CPU to repeat that exact loop 500 times to finish the whole job.

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