memory addressing

Question

Consider $1 \text{GHz}$ clock frequency processor,uses different operand accessing models shown below:

Operand Accessing Mode	Frequency(%)
Register	10
Immediate	20
Direct	30
Memory Indirect	20
Indexed	20

Assume that $2$ memory cycles consumed for memory reference ,3 cycles consumed for arithmetic computation and $1$ cycle consumed when the operand is in register(s) instruction itself . The average operand fetch rate (in millions $\text{words/sec}$) of processor is __________ (upto 2 to decimal places).

Answer 1

Operand Addressing Mode	Frequency	No of Cycles
register	$10 \%$	$1$-reg reference ( $1$ cycle)
immediate	$20 \%$	no reference ($0$ cycle)
direct	$30 \%$	$1$-mem reference ($2$ Cycle)
memory indirect	$20 \%$	$2$-mem reference ( $4$ Cycle)
indexed	$20 \%$	$1$-reg reference and $1$-mem reference and $1$-arithmetic calculation ($6$ Cycle)

In Indexed Addressing mode, if nothing specified then assume "Base Address is given directly into the instruction and Index value is stored into the Index Register".

Total average number of Cycle required  to execute one instruction = $ 1 * 0.1 + 0 * 0.2 + 2 * 0.3 + 4 * 0.2 + 6 * 0.2 $

= $ 2.7 $ Cycles

Cycle time = $ \frac{1}{1 GHz}  = 1 $ nano second.

Average time required to execute one instructions = $ 2.7 * 1 = 2.7 $ nano second. 

$2.7 $ nano second required for = $1$ instruction

$1$ second required for = $ \frac{1}{2.7 * 10^{-9}} $ instructions

                                 = $ 0.37037037037 *  10^{9} $ instructions

                                 = $ 370.37 * 10^{6} $ instructions

                                 = $370.37$ MIPS

Comments

Yes , I was also thinking for immediate It will be 0

Answer 2

operand addressing mode	frequency	cycles
register	10%	1
immediate	20%	1
direct	30%	2 (2 memory read cycles)
memory indirect	20%	4 (2 times 2 memory read cycles)
indexed	20%	5 (2 memory read cycles + 3 for index add)

Total number of cycle = $\frac{1*.1+1*.2+2*.3+4*.2+5*.2}{.1+.2+.3+.2+.2} = 2.7$

Cycle time = $\frac{1}{1Ghz} = 1ns$

1 operand -> 2.7 ns
       ?        ->1 sec    
Average fetch rate = $\frac{1}{2.7}  = .370370$ op/ns
                                                    = .370370 $10^9$op/s
                                                    = 370.37  MIPS

Comments

Could you please explain the cycle calculation in details for the given addressing modes.

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for index addressing we need 1 cycle for register + 3 for alu + 2 for memory acces

so total we need 6 cycles therfore total number of cycles will be 2.9

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@srestha @Shefali @lokesh @umang check my solution and let me know, if their is any thing, which you think is wrong.