Assuming all operands are initially in memory, 6 memory operations are (at least) required to fetch all operands.
Also assuming that every ALU instruction(data manipulation instructions) is such that the first address in the instruction is destination as well as address of first operand.
For eg : ADD R1, R2 means Register R1 is the destination as well as the address of first operand for addition operation.
Also assuming ** is exponentiation.
(So many assumptions.. very poorly framed question it is..But that year paper was subjective, so we could have assumed things and write what we assumed in the answer).
Now, we have two address machine, where each operand is either a register or a memory location.
Our first priority : Minimum memory accesses
Our Second priority : Minimum number of registers used.
So,
Let's bring operand 'a' into register r1 and let b stay in memory. So,
ADD r1,b (r1 <----a ; r1 <---- (r1+b))
MUL r1,c ( (r1 <---- (r1 * c)) )
So, Now r1 has (a+b)*c.
Let's bring operand e into register r2.
Exp r2, l
Let's bring operand d into register r3. (If it was $e^l/d$ then we would have not brought d into register But since d here is the first operand, we have to bring it to the register because first address in the instruction is destination as well as address of first operand.)
DIV r3,r2
SUB r1,r3
So, 3 registers.
NOTE that answer for expression
$(a+b)∗c− e^l/d$ would be 2 registers.