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Recent questions tagged circuit-output
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GO Classes DPP | Digital Logic | Canonical Normal Form | Philadelphia University
The logic circuit below has three inputs, $X$, $Y$, and $Z$, and two outputs, $F$ and $G$. Which of the below given minterm list for output $F$ is correct?$\Sigma(0,1,2,4...
GO Classes
667
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asked
Jun 12, 2025
Digital Logic
goclasses
digital-logic
circuit-output
canonical-normal-form
boolean-algebra
combinational-circuit
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GO Classes DPP | Digital Logic | Combinational Circuit | Philadelphia University
$$\text { If the input combination } \mathbf{A}=\mathbf{0}, \mathbf{B}=\mathbf{1} \text { is applied to this circuit, the (steady state) output will be: }$$$X=0, Y=0$ $\m...
GO Classes
517
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Jun 12, 2025
Digital Logic
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digital-logic
circuit-output
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GO Classes DPP | Digital Logic | Flip Flop | Philadelphia University
A sequential circuit with two $\mathbf{D}$ Flip-Flops, $\mathbf{A}$ and $\mathbf{B}$; two inputs, $\mathbf{x}$ and $\mathbf{y}$; and one output, $\mathbf{z}$, Which of th...
GO Classes
661
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asked
Jun 6, 2025
Digital Logic
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flip-flop
finite-state-machines
circuit-output
synchronous-asynchronous-circuits
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GO Classes DPP | Digital Logic | Flip Flop | Philadelphia University
When designing the circuit with the state table shown below using JK flip flops, then $\mathrm{Ja}=\ldots, \mathrm{Ka}=\ldots$$\mathrm{Ja}=\mathrm{B}, \mathrm{Ka}=\mathrm...
GO Classes
564
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asked
Jun 6, 2025
Digital Logic
goclasses
digital-logic
flip-flop
circuit-output
synchronous-asynchronous-circuits
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529
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GO Classes DPP | Digital Logic | Decoder | Philadelphia University
The circuit shown here is most likely a ______ .AdderMultiplexerDemultiplexerParity generator
GO Classes
529
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asked
Jun 6, 2025
Digital Logic
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digital-logic
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GO Classes DPP | Digital Logic | Decoder | Philadelphia University
What function $F(x, y, z)$ is implemented in the figure shown below?$F=\Sigma m(2,4,5)$$F=\Sigma m(3,5,6)$$F=\Sigma m(2,3,5)$$F=\Sigma m(3,4,6)$
GO Classes
691
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asked
Jun 3, 2025
Digital Logic
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decoder
circuit-output
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GO Classes DPP | Digital Logic | Multiplexer Output, Boolean Algebra| Philadelphia University
An 8-to-1 multiplexer has inputs $\mathbf{A}, \mathbf{B}$, and $\mathbf{C}$ connected to the selection inputs $\mathbf{S2}, \mathbf{S1}$, and $\mathbf{S0}$, respectively....
GO Classes
1.4k
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asked
May 31, 2025
Digital Logic
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GATE CSE 2025 | Set 2 | Question: 21
Consider the following logic circuit diagram.Which is/are the CORRECT option(s) for the output function $F$ ?$\overline{X Y}$$\overline{X}+\overline{Y}+X \overline{Y}$$\...
Arjun
8.1k
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asked
Feb 27, 2025
Digital Logic
gatecse2025-set2
digital-logic
circuit-output
multiple-selects
easy
one-mark
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ISRO CSE 2023 | Question: 29
The resulting logic circuit obtained when both inputs of NOR and NAND gates are connected together is:ANDXORORNOT
admin
978
views
asked
Sep 28, 2024
Digital Logic
isro-cse-2023
digital-logic
logic
circuit-output
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NIELIT 2021 Dec Scientist B - Section B: 73
The logic expression for the output of following circuit is:$\overline{\text{A}}\text{C}+\overline{\text{B}}\text{C}+\text{CD}$$\text{A}\overline{\text{C}}+\text{B}\overl...
admin
641
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asked
Jul 21, 2022
Digital Logic
nielit-2021-it-dec-scientistb
digital-circuits
circuit-output
nielit2021dec-scientistb
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923 views
UGC NET CSE | June 2005 | Part 2 | Question: 10
Identify the logic function performed by the circuit shownExclusive-$OR$$AND$Exclusive-$NOR$$NOR$
go_editor
923
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asked
Mar 26, 2020
Digital Logic
ugcnetcse-june2005-paper2
digital-circuits
logic
circuit-output
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ISRO CSE 2020 | Question: 66
The following circuit compares two $2$-bit binary numbers, $X$ and $Y$ represented by $X_1X_0$ and $Y_1Y_0$ respectively. ($X_0$ and $Y_0$ represent Least Significant Bit...
Satbir
7.1k
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asked
Jan 13, 2020
Digital Logic
isro-2020
digital-logic
digital-circuits
circuit-output
normal
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11 votes
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ISRO CSE 2020 | Question: 12
If $ABCD$ is a $4$-bit binary number, then what is the code generated by the following circuit?BCD codeGray code$8421$ codeExcess-$3$ code
Satbir
5.7k
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asked
Jan 13, 2020
Digital Logic
isro-2020
digital-logic
combinational-circuit
circuit-output
normal
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15 votes
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ISRO CSE 2020 | Question: 11
Minimum number of NAND gates required to implement the following binary equation$Y = (\overline{A}+\overline{B})(C+D)$$4$$5$$3$$6$
Satbir
11.5k
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asked
Jan 13, 2020
Digital Logic
isro-2020
digital-logic
combinational-circuit
circuit-output
normal
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ISRO CSE 2020 | Question: 77
Consider the following circuitThe function by the network above is$\overline{AB}E+EF+\overline{CD}F$$(\overline{E}+AB\overline{F})(C+D+\overline{F})$$(\overline{AB}+E)(\o...
Satbir
5.7k
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asked
Jan 13, 2020
Digital Logic
isro-2020
digital-logic
combinational-circuit
circuit-output
normal
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