GATE CSE 2019 | Question: 45

Question

A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept the starting address of the block, it then takes $3$ cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of $1$ word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is  ______$\times 10^6$ bytes/sec.

Comments

Bandwidth = data rate (they even gave the units)

Bytes = 32

Time = 1 + 3 + 8(1) cycles.

1 cycle = $\frac{1}{60*10^6}$ seconds.

So, bandwidth = $\frac{32*60*10^6}{12}$

So, 160

---

This is NPTEL assignment question.

And hamacher also has one question like this in the exercise.

---

Could anyone verify this, I think minimum time would have been without considering there is a miss in cache when reads request is served but since there is no info on it how cache would work so we assumed that there is a miss for every request so this is worst case speed system have right?

Answer 1

Time to transfer a cache block $ = 1+3+8 = 12$ cycles.

i.e., $4$ bytes $\times 8 = 32$ bytes in $12$ cycles.

So, memory bandwidth $ = \frac{32}{12 \text{ cycle time}} =\frac{32}{12/(60 \times 10^6)}= 160 \times 10^6 $ bytes/s

Comments

question says " maximum bandwidth for the memory system when the program running on the processor issues a series of read operations ". So in case of maximum bandwidth, shouldn't we consider a case of no miss in cache. In that case, i word that is 4 bytes will be transferred in 1 clock cycle. Therefore BW should be 240 in that case. Please correct me.

---

But we can't get rid of the first miss right? The first reference miss will be there at any cost.  Except for this miss, we got to take care that we don’t face any other miss.

---

Yes, there is exact matching with that lecture.

Answer 2

$\underline{\mathbf{Answer:}}\;\bbox[lightgreen, 5px, border: 2px solid black]{\color {black} {160 \times 10^6\; \frac{\mathrm {Bytes}}{\mathrm{sec}}}}$

$\underline{\mathbf{Explanation:}}$

$\text {Given frequency} = 60\ \text{MHz}$

This means that the processor completes $\color{green}{60\times 10^6 \;\text{cycles in}\;1 \;\text{second}}.$

$\therefore $ One cycle is completed in $\dfrac{1}{60\times 10^6 }\; \text{seconds}\;\;\text{[Using Unitary Method]}$

Now, To service a cache miss, number of cycles needed $$ \color{blue}{= 1\;\text{cylce}}\;\color{blue}{\text{(to accept starting address of the block)}} + 3\;\text{cylces}\;\color{blue}{\text{(to fetch all the $8$ words of the blocks)}}$$

$$+  \underbrace{8\times1}_\text{$\because$1 word per cycle}\;\text{cylces}\;\color{blue}{\text{(to transmit all $8$ words of the block)}}=  12  \;\text{cycles}$$

$\underline{\color{red}{\mathbf{Note:}}}$ Total data is the data which is used for trasmitting the words of the requested block at the rate of $\mathbf{1}$ word per cycle $=\mathbf{8\;words \times 4\;Byte\;(Size\; of\; each\; word)}$

$ \begin{align}\therefore \mathbf{Bandwidth} \require{cancel} &= \dfrac{\text{Total Data}}{12 \;\text{cycle time}} \\&= \dfrac{8\times4\;\text{Bytes}}{12\;\text{cycles }\times1\; \text{cycle time}} \\&= \dfrac{32}{12 \times \dfrac{1}{60\times10^6}} \\&= \require{cancel} \dfrac{32\times \cancel {60}^{5} \times 10^6}{\cancel{12}^1}\\& = 5 \times 32 \times {10}^6 \\&= \color {black}{160 \times 10^6 \; \dfrac{\text{Bytes}}{\mathrm{sec}}}\end{align}$

$\therefore  \bbox[lightgreen, 5px, border: 2px solid black]{\color {black}{160 \times 10^6 \; \dfrac{\text{Bytes}}{\mathrm{sec}}}}$ is the correct answer.

Comments

Great!

Answer 3

$Cache\ block = 8\ words$

$Word\ size = 4\ bytes$

$Cache\ block\ size = 32\ bytes$

$frequency = 60\ MHz$

$Cycle\ time(\#\ of seconds/cycle) = \dfrac{1}{frequency} = \dfrac{1}{60×10^6} seconds$

$Cache\ miss\ time:$

$1\ cycle(Address\ of\ the\ block)$

$3\ cycles (fetch\ all\ the\ 8-words\ of\ the\ block)$

$8\ cycles (transfer\ of\ 8-words\ at\ the\ rate\ of\ 1\ cycle/word )$

$Total = 12\ cycles$

$Total\ time= \dfrac{12}{60×10^6}sec$

$Total\ bandwidth = \dfrac{total\ data}{total\ time} = \dfrac{32\ bytes}{\dfrac{12}{60×10^6}} = 160 × 10^6 bytes/second$

$Answer: 160$

Comments

Good answer.

Just edit it little more.

From bottom $3^{rd}$ lin is $10^6$

---

Done editing.

Thank you.

---

जबरदस्त।🛡️🤩

Answer 4

My approach:

Total cycles = 1+3+8 =12

This way I got it as 160 bps

Plzx confirm :0

Comments

I too followed the same procedure and got the answer 160

---

is 160 the write answer please someone confirm

---

I think that was correct....what is ur answer

---

Yeah I did it 160

---

@Markzuck but the maximum bandwidth can be 240 if there is no cache miss

---

@rajatshukla2910Yes, I am worried about such cases.

---

160 is for cache miss case only....if cache hit happens ,only 1 word will be transferred but not entire block.....this is my view....sry if I m wrong

---

by this approach it should be 166.6

---

since it is written series of read operation I assume(prohibited in gate exam) that program is of video application hence data would be distinct so every time after 12 cycle there would be miss . Just hope for the best

---

Yeah , according to this  answer should be 240 since cpi =8 ( 1word)

---

It is given series of read operations, so i think cpi would be 8 cycles since pipelining is used, so answer should be 240