Here we have to keep in mind the phrase:
A non-pipelined single cycle processor
This signifies that instruction in a non pipelined scenario is incurring only a single cycle to execute entire instruction. Hence no concept of stage comes in case of single cycle non pipelined system.
The cycle time can be calculated from clock frequency given in non pipelined system $=100\text{ MHz}$
Therefore clock cycle time in non pipelined system $=\dfrac{1}{(100\times 10^6)} \text{s} =10 \text{ ns}$
Now cycle time in pipelined system $=\text{max(stage delay + interface delay)}$
$=2.5 + 0.5 =3\text{ ns}$
Therefore,
Speedup $=\dfrac{\text{CPI}_{\text{non pipeline}}\times \text{Cycle time}_{\text{non pipeline}}}
{(\text{CPI}_{\text{pipeline}}\times \text{Cycle time}_{\text{pipeline}})}$
$=\dfrac{1\times 10}{(1\times 3)} =3.33$
[Since in case of non pipeline we have single cycle processor, so $\text{CPI}_{\text{non pipeline}}=1 \text{ and } \text{CPI}_{\text{pipeline}}$ by default $=1$]
Hence, (C) is the correct answer.