GATE IT 2006 | Question: 79

Question

A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX stage. The sequence of instructions corresponding to the statement $X = (S - R * (P + Q))/T$ is given below. The values of variables $P, Q, R, S$ and $T$ are available in the registers $R0, R1, R2, R3$ and $R4$ respectively, before the execution of the instruction sequence.

$$\begin{array}{lll}  \text{ADD} & \text{$R5,R0,R1$} & \text{$;R5$} \leftarrow \text{R0 + R1} \\
\text{MUL}& \text{$R6,R2,R5$} & \text{$;R6$} \leftarrow \text{R2 * R5} \\
 \text{SUB} &  \text{$R5,R3,R6$} & \text{$;R5$} \leftarrow \text{R3 -R6}  \\ 
\text{DIV} &\text{$R6,R5,R4$} & \text{$;R6$} \leftarrow \text{R5/R4} \\
\text{STORE} &\text{$R6,X$}& \text{$;X$} \leftarrow \text{R6}  \\
\end{array}$$

The IF, ID and WB stages take 1 clock cycle each. The EX stage takes $1$ clock cycle each for the ADD, SUB and STORE operations, and $3$ clock cycles each for MUL and DIV operations. Operand forwarding from the EX stage to the ID stage is used. The number of clock cycles required to complete the sequence of instructions is

• A. $10$
• B. $12$
• C. $14$
• D. $16$

Comments

Please someone change the direction of arrows in the instructions shown in this question.

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It's $4-$ stage pipeline.  Memory access phase of RISC architecture is implicitly included in $EX$ stage so split phase can be safely assumed.

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similar

https://gateoverflow.in/1235/gate2007-37-isro2009-37

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Can anyone please confirm whether @2019_Aspirant comment is true or not ?

Because what I know is split phase is independent of operand forwarding and split phase doesn’t depend on any architecture (in accordance to the GATE PYQ’s solved). We can safely use split-phase here irrespective of whether it’s mentioned that operand forwarding is used or not. Another point is I have read that operand forwarding needs independent cycles to occur, unlike split-phase wherein a single cycle (using rising edge and falling edge) we can implement it(split phase). So, what I think is that this question has no significance of the line operand forwarding because if it’s mentioned or not, still we will use the split-phase, which gives us the required result. @Arjun Sir, @Bikram Sir.

Answer 1

$$\small \displaystyle \begin{array}{|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline &C_1&C_2&C_3&C_4&C_5&C_6&C_7&C_8&C_9&C_{10}&C_{11}&C_{12}\\\hline
\textbf{ADD}&\text{IF}&\text{ID}&{\color{green}{\underset{\boxed{1}}{\text{EX}}}}&\text{WB}&&&&&&&&\\\hline
\textbf{MUL}&&\text{IF}&{\color{green}{\underset{\boxed{1}}{\text{ID}}}}&\text{EX}&\text{EX}&{\color{green}{\underset{\boxed{1}}{\text{EX}}}}&\text{WB}&&&&&\\\hline
\textbf{SUB}&&&\text{IF}&\color{red}{-}&\color{red}{-}&{\color{green}{\underset{\boxed{1}}{\text{ID}}}}&{\color{green}{\underset{\boxed{1}}{\text{EX}}}}&\text{WB}&&&&\\\hline
\textbf{DIV}&&&&&&\text{IF}&{\color{green}{\underset{\boxed{1}}{\text{ID}}}}&\text{EX}&\text{EX}&{\color{green}{\underset{\boxed{1}}{\text{EX}}}}&\text{WB}&\\\hline
\textbf{STORE}&&&&&& &\text{IF}&\color{red}{-}&\color{red}{-}&{\color{green}{\underset{\boxed{1}}{\text{ID}}}}&\text{EX}&\text{WB}\\\hline \end{array} $$

$\color{red}{-}\quad\text{Stalls}$
$\color{green}{\boxed{1}} \quad \text{Operand forwarding from EX-ID using split phase}$

So, answer is 12.

Correct Answer: $B$

Reference

Comments

http://web.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/forward.html

For more details

 

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@prajjwalsingh_11

Plz can you provide exact link. i am not able to get the exact content.

 

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Ajinkya9 https://web.archive.org/web/20210506092429/http://web.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/forward.html

Use archived links.

Answer 2

answer = option D = $16$ cycles are required

Comments

@Arjun sir i think that question given in 2015 is a typo and they might have overlooked it split phase has got nothing to do with forwarding  we cannot assume things suppose if only one clock cycle is given for execute phase we are generally supposed to make writes at the rising edge then from where will it perform the actual execution of the operation if it writes the result directly in the rising edge so the answer here is 12  using operand forwarding, by default i only say WB AND RD PHASE CAN OCCUR IN THE SAME CLOCK CYCLE ONE IN THE RISING EDGE(WB) AND THE OTHER IN FALLING EDGE (RD) IN EVERY NPTEL LECTURE ON COA they r using the same example

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when to use EX to EX and EX to ED
someone reply fast. Just few hours are left for Gate 19

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http://web.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/forward.html

For more details

 

Answer 3

Hi  , I have a very silly doubt here. 

Can we do the IF stage as I did ? because in other answers I could see , IF is also done after EX

amarVashishth 

srestha goel 

I have the confusion here that , IF stage of I4 instruction , can I start it in clock 4 ? because anyhow , ID should be started at  clock 7. or does IF also needs to start at clock 6 ?

Please clarify this doubt.

(N.B : please bear with my poor , illegible hand-writing )

Comments

Answer given to this question is 14

Answer 4

12 clocks