The instruction pipeline of RISC processor has 200 instruction in which 100 are performing addition, 25 performing division and 75 are performing multiplication, where Execution state for addition take 1 clock, multiplication take 3 clock cycles and division take 5 clock cycles. Assume pipeline has 5 stages IF, ID EX, MA and WB and their is no data and control hazard. The number of clock cycles required for execution of sequence of instruction are ________.
my ans is 354 where iam wrong.
approch totel 200 in which (100 add having 1 cc) +(25*5-1) +(75*(3-1))=354