Option D)All Of The Above.
Pipeline suffer from options:-
A) Yes, As pipeline need to work in SYNC all stage should operate in same time. If there are stages taking different time, if there is a slower stage, all faster stage will be bottlenecked by the cycles the slowest stage takes.
B)Yes, As there could be DATA HAZARDS.
eg: SUB R2,R4,R5
ADD R6,R2,R4 //here register r2 result will be dependent on first instruction.
C)Yes, IF(Instruction Fetch) and MEM(Main Memory) stage can cause STRUCTURAL HAZARDS and there may be a chance that both stages need Memory simultaneously, that's why many Arch. slipt the cache as INST cache and Data Cache.