Number of transfers [i.e. each of 16 byte in one cycle.]= $\frac{2048}{16} = \frac{2^{11}}{2^{4}} = 128$ transfers Each of 16B
Time for Bus Cycle $\frac{1}{100MHz} = 10 ns$ .
Time for reading 128 transfer packets = 128 $\times$ 80ns = 10240 ns
Since access time of bus is overlapped with memory acess time. Pipelining is used so All 10 ns time is overlapped with 80 ns time But for lat 16 B take 10 ns time more = 10 + 80 = 90ns.
10240 + 90 = 10330ns
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If no pipelining then 128 $\times$ (10 +80) = 11520ns
Time saved using pipeline = 11520 - 10330 = 1190ns