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Recent questions tagged ram
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UGCNET CSE December 2022: 44
Which of the following is/are true for Dynamic $\text{RAM (DRAM)}$?It is slower than static $\text{RAM(SRAM)}$Packing Density is higher than Static $\text{RAM (SRAM)}$It ...
admin
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May 20, 2023
Others
ugcnetcse-dec2022
memory-management
ram
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Morris Mano Edition 3 Exercise 7 Question 37 (Page No. 305)
An integrated circuit ram chip has a capacity of 1024 words of 8 bits each ($1K \times 8$)How many addresses and the data lines are there in the chips?How many chips are ...
ajaysoni1924
505
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asked
Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
memory-unit
ram
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533
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Morris Mano Edition 3 Exercise 7 Question 36 (Page No. 305)
A computer uses RAM chips of $1024 \times 1$ capacity.how many chips are needed and how should there address line should be connected to provide a memory capacity of 1024...
ajaysoni1924
533
views
asked
Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
memory-unit
ram
descriptive
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856
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Morris Mano Edition 3 Exercise 7 Question 35 (Page No. 305)
How many $128 \times 8$ RAM chips are needed to provide a memory capacity of 2048 bytes?How many lines of the address must be used to access 2048 bytes? How many of these...
ajaysoni1924
856
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asked
Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
memory-unit
ram
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1
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1.7k
1.7k views
UGC NET CSE | December 2008 | Part 2 | Question: 41
In which of the following, ready to execute processes must be present in $RAM$ ?multiprocessing multiprogramming multitasking all of the above
rishu_darkshadow
1.7k
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asked
Sep 26, 2017
Operating System
ugcnetcse-dec2008-paper2
operating-system
ram
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0 votes
1
1 answer
1.9k
1.9k views
Computer Organization- Memory Addressing
For 16 bit address-bus, if an 8 K RAM chip is selected when $A_{13}, A_{14}$ and $A_{15}$ address bits are all one, then what is the range of the memory address?Options -...
Devwritt
1.9k
views
asked
Apr 12, 2017
CO & Architecture
co-and-architecture
ram
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10
10 votes
1
1 answer
7.3k
7.3k views
GATE CSE 1990 | Question: 4-i
State whether the following statements are TRUE or FALSE with reason:RAM is a combinational circuit and PLA is a sequential circuit.
Misbah Ghaya
7.3k
views
asked
Nov 23, 2016
Digital Logic
gate1990
true-false
digital-logic
ram
pla
non-gatecse
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5
5 votes
2
2 answers
3.8k
3.8k views
GATE CSE 1987 | Question: 1-ix
The refreshing rate of dynamic RAMs is in the range of$2$ microseconds$2$ milliseconds.$50$ milliseconds$500$ milliseconds
Misbah Ghaya
3.8k
views
asked
Nov 8, 2016
CO & Architecture
gate1987
co-and-architecture
ram
out-of-gatecse-syllabus
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0
0 votes
1
1 answer
1.1k
1.1k views
MadeEasy Test Series: Digital Logic - Ram
A RAM chip has 32 rows and 16 columns each with a single bit. The number of address line input required to gain unique addressing to every location is __________ .
khushtak
1.1k
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asked
Jan 28, 2016
CO & Architecture
made-easy-test-series
digital-logic
ram
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0
0 votes
2
answers
2 answers
4.6k
4.6k views
Computer Organization Question
A computer with 32-bit wide data bus uses 4 K x 8 static RAM memory chips. The smallest memory this computer can have is:(a) 32 kb (b) 16 kb (c) 8 kb (d) 24 kb
spawndon
4.6k
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asked
Jan 12, 2016
CO & Architecture
ram
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2 answers
22.3k
22.3k views
How many 256 X 4 RAM chips are needed to organize a memory of capacity of 32KB?
Shefali
22.3k
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asked
Aug 8, 2015
CO & Architecture
co-and-architecture
memory-interfacing
ram
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5
5 votes
2
answers
2 answers
21.2k
21.2k views
How many 2K x 8 RAM chips are needed?
We want to build a memory with 4-byte words and a capacity of 221 bits. How many 2K x 8 RAM chips are needed? How many address lines are needed for the memory? How many o...
Supromit Roy
21.2k
views
asked
Dec 1, 2014
CO & Architecture
memory-interfacing
ram
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