Questions by aaliya / GATE Overflow for GATE CSE

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Incomplete Recursive definition
Suppose an array A={a1,a2, an} contains a set of n distinct coins types where each ai € N for 1<=n. Suppose also that a1<a2<a3 <an the coin hanging problem is defined as follows: Given W € N , find the smallest numbers of coins from A that adds upto W, ... 0 if j=0 =∞ if i=0 and j≠0 =expr1 if i,j>0 and j<a[i] =expr2 if i,j>0 and a[i]<=j

Suppose an array A={a1,a2,…………an} contains a set of n distinct coins types where each ai € N for 1<=n. Suppose also that a1<a2<a3……………<an the coin han...

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asked Aug 18, 2017

4 votes

1 answer

2

doubt in time complexity
Given a 2-D array A with n rows and k columns initialized to -1 . what is the Time complexity of f(A,m,m)? int f(int **a, int n, int k) { if((n<=k)|| (k<=1)) return 1; if(a[n][k]==-1) a[n][k]=f(a,n-1,k)+f(a,n-1,k-1); return a[n][k]; } how to write recurrence relation for this

Given a 2-D array A with n rows and k columns initialized to -1 . what is the Time complexity of f(A,m,m)?int f(int a, int n, int k){if((n<=k)|| (k<=1)) return 1;if(a[n]...

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asked Aug 17, 2017

1 votes

0 answers

3

latency of retrieving a cache block starting at address zero from main memory is ?
A cpu has cache with block size 64B . the main memory has k- banks , each bank being C-byte wide. Consecutive C-byte chunks are mapped on consecutive banks with wraparound. All the K –banks can be ... c=2 and k=24, then latency of retrieving a cache block starting at address zero from main memory is ?

A cpu has cache with block size 64B . the main memory has k- banks , each bank being C-byte wide. Consecutive C-byte chunks are mapped on consecutive banks with wraparoun...

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asked Aug 16, 2017

1 votes

0 answers

4

How many data cache misses will occur in total
Consider a machine with a byte addressable main memory of 216 bytes. Assume that a direct mapped data cache consisting of 32 lines of 64 byte each is used in the system. A 50* 50 2-d array of bytes is stored in the mm starting ... the contents of the data cache do not change in between the two accesses. How many data cache misses will occur in total?

Consider a machine with a byte addressable main memory of 216 bytes. Assume that a direct mapped data cache consisting of 32 lines of 64 byte each is used in the system. ...

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asked Aug 16, 2017

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title	title:apple
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views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
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