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Recent activity by astha
11
answers
1
GATE CSE 2016 Set 1 | Question: 35
What will be the output of the following $C$ program? void count (int n) { static int d=1; printf ("%d",n); printf ("%d",d); d++; if (n>1) count (n-1); printf ("%d",d); } void main(){ count (3); } $3 \ 1 \ 2 \ 2 \ 1 \ 3 \ 4 \ 4 \ 4$ $3 \ 1 \ 2 \ 1 \ 1 \ 1 \ 2 \ 2 \ 2$ $3 \ 1 \ 2 \ 2 \ 1 \ 3 \ 4$ $3 \ 1 \ 2 \ 1 \ 1 \ 1 \ 2$
What will be the output of the following $C$ program?void count (int n) { static int d=1; printf ("%d",n); printf ("%d",d); d++; if (n>1) count (n-1); printf ("%d",d); } ...
15.7k
views
commented
Jan 27, 2017
Programming in C
gatecse-2016-set1
programming-in-c
recursion
normal
+
–
1
answer
2
GATE CSE 1990 | Question: 4-iv
Transferring data in blocks from the main memory to the cache memory enables an interleaved main memory unit to operate unit at its maximum speed.True/False.Explain.
Transferring data in blocks from the main memory to the cache memory enables an interleaved main memory unit to operate unit at its maximum speed.True/False.Explain.
4.4k
views
commented
Sep 6, 2016
CO and Architecture
gate-1990
true-false
co-and-architecture
cache-memory
memory-interleaving
+
–
8
answers
3
GATE CSE 2016 Set 1 | Question: 32
The stage delays in a $4$-stage pipeline are $800, 500, 400$ and $300$ picoseconds. The first stage (with delay $800$ picoseconds) is replaced with a functionality equivalent design involving two stages with respective delays $600$ and $350$ picoseconds. The throughput increase of the pipeline is ___________ percent.
The stage delays in a $4$-stage pipeline are $800, 500, 400$ and $300$ picoseconds. The first stage (with delay $800$ picoseconds) is replaced with a functionality equiva...
25.8k
views
commented
Aug 29, 2016
CO and Architecture
gatecse-2016-set1
co-and-architecture
pipelining
normal
numerical-answers
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