1 votes 1 votes What is the division factor of the given clock divider circuit? $2$ $3$ $1.5$ $2.5$ Digital Logic isro2013-ece isro-ece digital-logic sequential-circuit flip-flop + – sh!va asked Feb 27, 2017 • edited Dec 4, 2022 by Lakshman Bhaiya sh!va 1.6k views answer comment Share Follow See all 0 reply Please log in or register to add a comment.
Best answer 1 votes 1 votes Now the clock period as can be seen has doubled, which implies frequency is divided by 2. So answer is A)2 Rahul Jain25 answered Mar 4, 2017 • selected Mar 6, 2017 by Rahul Jain25 Rahul Jain25 comment Share Follow See all 3 Comments See all 3 3 Comments reply Rahul Jain25 commented Mar 4, 2017 reply Follow Share And duty cycle is 25% , is that correct??? Bcoz only 25% time of clk single cycle it is in set condition??? 1 votes 1 votes sh!va commented Mar 6, 2017 reply Follow Share Yes.. seems duty cycle is 25% 1 votes 1 votes KrishnaGupta commented Jun 23, 2023 reply Follow Share @Rahul Jain25 @Lakshman Bhaiya, kindly check below my understanding:Let initially Q1’ be 1 and Q2’ be 1. During the first clock high, Q1’ will occillate 101010…. we are not sure at which state it will stop (it is dependent on time taken by FF). Thus CLK_OUT will also be 101010..During first clock low, if Q1’ is 1. Q2’ will occillate 1010101… here also we are not sure where it will stop. Thus CLK_OUT will also be 101010…During first clock low, if Q1’ is 0. Q2’ will occillate 1010101.. CLK_OUT will be 0.This will repeat for every cycle. 0 votes 0 votes Please log in or register to add a comment.