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Consider below sequence of instructions

$1.lw\,s2,0(s1)$

$2.lw\,s1,40(s6)$

$3.sub\,s6,s1,s2$

$4.add\,s6,s2,s2$

$5.or\,s3,s6,0$

$6.sw\,s6,50(s1)$

What is the number of clock cycles taken by above set of instructions when executed on 5-stage MIPS architecture(IF,ID,EX,MA,WB)

(a)Without operand forwarding

(b)With operand forwarding.

My Answers

(a)16 cycles

(b)11 cycles

Are my answers correct?

Source:https://cseweb.ucsd.edu/classes/wi12/cse141-a/solutions/assignment5-soln.pdf

Question 3, part 3 and 4.

1 Answer

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Without operand forwarding

IF ID EX MA WB                            
  IF ID EX MA WB                          
    IF       ID EX MA WB                  
            IF       ID EX MA WB          
                    IF       ID EX MA WB  
                            IF ID EX MA WB

Without operand forwarding (but we can minimize it with split phase)


With split phase without operand forwarding 

IF ID EX MA WB                      
  IF ID EX MA WB                    
    IF     ID EX MA WB              
          IF ID EX MA WB            
            IF     ID EX MA WB      
                  IF ID EX MA WB    

 

Here Split Phase :WB-ID

And stalls occurs due to

1.lw s2,0(s1)

2.lw s1,40(s6)

3.sub s6,s1,s2

4.add s6,s2,s2

5.or s3,s6,0

6.sw s6,50(s1)

So, without operand forwarding=14 clock cycles

 


With operand forwarding in EX-EX stage

IF ID EX MA WB              
  IF ID EX MA WB            
    IF ID   EX MA WB        
      IF   ID EX MA WB      
          IF ID EX MA WB    
            IF ID EX MA WB  

With operand forwarding=11 clockcycles


Ref:https://gateoverflow.in/1391/gate2005-68

https://gateoverflow.in/186403/coa-pipeline

edited by

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