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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

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Highest voted questions in CO and Architecture

#141
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GATE CSE 2007 | Question: 73
Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ are the general purpose registers.$$\begin{array}{|l|l|l|c|} \hline & \text {Instruction} & \...
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#142
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1 answers
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GATE IT 2007 | Question: 39
Data forwarding techniques can be used to speed up the operation in presence of data dependencies. Consider the following replacements of LHS with RHS. $R1→ Loc, Loc→...
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#143
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3 answers
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GATE CSE 2002 | Question: 2.6, ISRO2008-19
The performance of a pipelined processor suffers if:the pipeline stages have different delaysconsecutive instructions are dependent on each otherthe pipeline stages share...
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#144
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2 answers
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GATE CSE 2001 | Question: 9
A CPU has $32-bit$ memory address and a $256 \ KB$ cache memory. The cache is organized as a $4-way$ set associative cache with cache block size of $16$ bytes.What is the...
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#145
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8 answers
29 votes
GATE CSE 2017 Set 2 | Question: 53
Consider a machine with a byte addressable main memory of $2^{32}$ bytes divided into blocks of size $32$ bytes. Assume that a direct mapped cache having $512$ cache line...
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#146
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3 answers
29 votes
GATE CSE 2003 | Question: 49
Consider the following assembly language program for a hypothetical processor $A, B,$ and $C$ are $8$ bit registers. The meanings of various instructions are shown as com...
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#147
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5 answers
29 votes
GATE CSE 2016 Set 2 | Question: 10
A processor has $40$ distinct instruction and $24$ general purpose registers. A $32$-bit instruction word has an opcode, two registers operands and an immediate operand. ...
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#148
8.9k
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4 answers
29 votes
GATE CSE 2015 Set 3 | Question: 14
Consider a machine with a byte addressable main memory of $2^{20}$ bytes, block size of $16$ bytes and a direct mapped cache having $2^{12}$ cache lines. Let the addresse...
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#149
7.9k
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3 answers
28 votes
GATE CSE 1999 | Question: 1.22
The main memory of a computer has $2\;\text{cm}$ blocks while the cache has $2\;\text{c}$ blocks. If the cache uses the set associative mapping scheme with $2$ blocks per...
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#150
8.6k
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2 answers
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GATE CSE 2000 | Question: 1.10
The most appropriate matching for the following pairs$$\begin{array}{ll} \text{X: Indirect addressing} & \text{1: Loops } \\ \text{Y: Immediate addressing } & \text{2: P...
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#151
4.2k
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3 answers
27 votes
GATE CSE 1988 | Question: 2-ii
Using an expanding opcode encoding for instructions, is it possible to encode all of the following in an instruction format shown in the below figure. Justify your answer...
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#152
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2 answers
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Hamacher-DMA
The average seek time and rotational delay in a disk system are 6ms and 3ms, respectively. The rate of data transfer to or from the disk is 30 Mbytes/sec and all disk ac...
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#153
7.4k
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2 answers
27 votes
GATE IT 2006 | Question: 43
A computer system has a level-$1$ instruction cache ($1$-cache), a level-$1$ data cache ($D$-cache) and a level-$2$ cache ($L2$-cache) with the following specifications:\...
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#154
6.9k
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1 answers
27 votes
GATE CSE 2005 | Question: 66
Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side.$$\begin{array...
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#155
6.0k
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3 answers
26 votes
GATE CSE 1987 | Question: 4a
Find out the width of the control memory of a horizontal microprogrammed control unit, given the following specifications:$16$ control lines for the processor consisting ...
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#156
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4 answers
26 votes
GATE CSE 2009 | Question: 8, UGCNET-June2012-III: 58
A CPU generally handles an interrupt by executing an interrupt service routine:As soon as an interrupt is raised.By checking the interrupt register at the end of fetch cy...
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#157
11.8k
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3 answers
25 votes
GATE CSE 2021 Set 2 | Question: 20
Consider a computer system with $\text{DMA}$ support. The $\text{DMA}$ module is transferring one $8$-bit character in one $\text{CPU}$ cycle from a device to memory thro...
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#158
16.9k
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4 answers
25 votes
GATE CSE 2020 | Question: 43
Consider a non-pipelined processor operating at $2.5$ GHz. It takes $5$ clock cycles to complete an instruction. You are going to make a $5$- stage pipeline out of this p...
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#159
29.2k
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6 answers
25 votes
GATE CSE 2020 | Question: 44
A processor has $64$ registers and uses $16$-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a re...
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#160
6.4k
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1 answers
25 votes
GATE IT 2005 | Question: 45
A hardwired CPU uses $10$ control signals $S_1$ to $S_{10}$, in various time steps $T_1$ to $T_5$, to implement $4$ instructions $I_1$ to $I_4$ as shown below:$$\begin{ar...
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