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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

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Highest voted questions in CO and Architecture

44 votes
5 answers
81
GATE CSE 2001 | Question: 1.7, ISRO2008-18
More than one word are put in one cache block to: exploit the temporal locality of reference in a program exploit the spatial locality of reference in a program reduce the miss penalty none of the above
More than one word are put in one cache block to:exploit the temporal locality of reference in a programexploit the spatial locality of reference in a programreduce the m...
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42 votes
2 answers
86
GATE IT 2006 | Question: 42
A cache line is $64$ bytes. The main memory has latency $32$ $ns$ and bandwidth $1$ $GBytes/s$. The time required to fetch the entire cache line from the main memory is: $32$ $ns$ $64$ $ns$ $96$ $ns$ $128$ $ns$
A cache line is $64$ bytes. The main memory has latency $32$ $ns$ and bandwidth $1$ $GBytes/s$. The time required to fetch the entire cache line from the main memory is:$...
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41 votes
4 answers
92
GATE CSE 2004 | Question: 20
Which of the following addressing modes are suitable for program relocation at run time? Absolute addressing Based addressing Relative addressing Indirect addressing I and IV I and II II and III I, II and IV
Which of the following addressing modes are suitable for program relocation at run time?Absolute addressingBased addressingRelative addressingIndirect addressingI and IVI...
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41 votes
11 answers
93
GATE CSE 2006 | Question: 09, ISRO2009-35
A CPU has $24$-$bit$ instructions. A program starts at address $300$ (in decimal). Which one of the following is a legal program counter (all values in decimal)? $400$ $500$ $600$ $700$
A CPU has $24$-$bit$ instructions. A program starts at address $300$ (in decimal). Which one of the following is a legal program counter (all values in decimal)?$400$$500...
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40 votes
3 answers
97
GATE IT 2006 | Question: 40
The memory locations $1000,1001$ and $1020$ have data values $18,1$ and $16$ ... value $20$ Memory location $1020$ has value $20$ Memory location $1021$ has value $20$ Memory location $1001$ has value $20$
The memory locations $1000,1001$ and $1020$ have data values $18,1$ and $16$ respectively before the following program is executed.$$\begin{array}{ll} \text{MOVI} & \text...
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40 votes
4 answers
98
GATE CSE 1998 | Question: 1.19
Which of the following addressing modes permits relocation without any change whatsoever in the code? Indirect addressing Indexed addressing Base register addressing PC relative addressing
Which of the following addressing modes permits relocation without any change whatsoever in the code?Indirect addressingIndexed addressingBase register addressingPC relat...
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