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Search results for clock-frequency
1
votes
2
answers
1
GATE Overflow | Mock GATE | Test 1 | Question: 60
A program runs in $20s$ in machine A with a clock speed of $200MHz$. A computer architecture wants to build a machine B which will run this program in $6$ seconds. The architect has delivered that a substantial increase in clock rate is ... clock cycles as machine A for this program. What clock rate should be targeted for a best design? (In $MHz$)
A program runs in $20s$ in machine A with a clock speed of $200MHz$. A computer architecture wants to build a machine B which will run this program in $6$ seconds. The a...
Ruturaj Mohanty
1.1k
views
Ruturaj Mohanty
asked
Dec 27, 2018
CO and Architecture
go-mockgate-1
numerical-answers
clock-cycles
clock-frequency
co-and-architecture
+
–
6
votes
2
answers
2
Q26 ch-5 M_E workbook
suppose that in 1000 memory reference there are 40 misses in the first level cache and 20 misses in the second level cache. Assume miss penalty from the L2 cache to memory is 100 cycles the hit time of the L2 cache is 10 clock cycles.the hit time of ... reference per instruction) x (miss rate) x (miss penalty) right?? so which miss rate and miss penalty should i put here?
suppose that in 1000 memory reference there are 40 misses in the first level cache and 20 misses in the second level cache. Assume miss penalty from the L2 cache to memor...
khushtak
12.5k
views
khushtak
asked
Oct 27, 2015
CO and Architecture
co-and-architecture
cache-memory
clock-frequency
clock-cycles
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–
2
votes
2
answers
3
Q-20 (control unit design) madeEasy workBook 2015
Show below are sements of a code run on a CISC and RISC archy separately CISC RISC MOV AX,05 MOV AX,00 MOV BX,06 MOV BX,05 MUL AX,BX MOV CX,06 start:ADD AX,BX loop loop start; loop till CX=0 If the MUL instruction takes 40 clock cycles, ... 2.8 (c) The CISC code runs slower by a factor of 0.025 (d) The RISC code will run faster by a factor of 40
Show below are sements of a code run on a CISC and RISC archy separatelyCISC RISCMOV AX,05 ...
khushtak
2.2k
views
khushtak
asked
Oct 7, 2015
CO and Architecture
clock-frequency
co-and-architecture
cisc-risc-architecture
+
–
3
votes
1
answer
4
Maximum Clock Rate
Delay of AND gate = 1ns, FF = 2ns. What is the maximum clock rate possible to apply so that counter will work satisfactorily? a) 143 MHz b) 200 MHz c) 333 MHz
Delay of AND gate = 1ns, FF = 2ns.What is the maximum clock rate possible to apply so that counter will work satisfactorily?a) 143 MHzb) 200 MHzc) 333 MHz
Tuhin Dutta
966
views
Tuhin Dutta
asked
Jan 18, 2018
Digital Logic
digital-logic
clock-frequency
+
–
1
votes
1
answer
5
Virtual Gate Test Series: Digital Logic - Flip Flop Delay
Sheshang
552
views
Sheshang
asked
Jan 18, 2017
Digital Logic
digital-logic
clock-frequency
flip-flop
virtual-gate-test-series
+
–
0
votes
1
answer
6
C pipelining
4 stage pipeline with respective delays of 2 ns , 8 ns , 3 ns , 1 ns .It is enhanced to improve the performance with stages , but in the enhancement process longest delay stage is decomposed into 2 equal delays . What is the clock frequency in the enhanced pipeline? please explain a bit..
4 stage pipeline with respective delays of 2 ns , 8 ns , 3 ns , 1 ns .It is enhanced to improve the performance with stages , but in the enhancement process longest dela...
hitendra singh
619
views
hitendra singh
asked
Dec 21, 2018
CO and Architecture
co-and-architecture
pipelining
clock-frequency
+
–
0
votes
0
answers
7
DLD maximum clock frequency doubt
How to approach this kind of problem ?please provide the detailed approach .
How to approach this kind of problem ?please provide the detailed approach .
Bhupendra
708
views
Bhupendra
asked
Dec 21, 2018
Digital Logic
digital-logic-clock-frequency
+
–
0
votes
0
answers
8
TANCET 2017 CLOCK FREQUENCY
Balaji Jegan
171
views
Balaji Jegan
asked
Oct 23, 2018
CO and Architecture
tancet2017
co-and-architecture
clock-frequency
+
–
2
votes
1
answer
9
Clock frequency required for proper operation of ripple counter
An 8 stage ripple counter uses a flip flop with propagation delay of 75 ns. The pulse width of strobe is 50ns. The frequency of input signal which can be used for proper operation of counter is? (A) 1 MHz (B) 500 MHz (C) 1.5 MHz (D) 2 MHz
An 8 stage ripple counter uses a flip flop with propagation delay of 75 ns. The pulse width of strobe is 50ns. The frequency of input signal which can be used for proper ...
GateAspirant999
8.0k
views
GateAspirant999
asked
Oct 17, 2016
Digital Logic
digital-logic
clock-frequency
digital-counter
+
–
0
votes
2
answers
10
Output clock frequency
Parshu gate
2.3k
views
Parshu gate
asked
Dec 6, 2017
Digital Logic
digital-logic
clock-frequency
digital-counter
+
–
1
votes
0
answers
11
maximum clock rate
What is the maximum clock rate possible to apply so that counter will work satisfactorily? a) 143 MHz b) 200 MHz c) 333 MHz
What is the maximum clock rate possible to apply so that counter will work satisfactorily?a) 143 MHzb) 200 MHzc) 333 MHz
Tuhin Dutta
475
views
Tuhin Dutta
asked
Jan 18, 2018
Digital Logic
digital-logic
clock-frequency
+
–
9
votes
1
answer
12
Counters+Frequency
___________ $\text{kHz}$ is the sum of frequencies at the points $a, b,c \text{ and } d$.
___________ $\text{kHz}$ is the sum of frequencies at the points $a, b,c \text{ and } d$.
Rahul Jain25
6.8k
views
Rahul Jain25
asked
Oct 13, 2016
Digital Logic
digital-logic
digital-counter
clock-frequency
+
–
0
votes
0
answers
13
MadeEasy Subject Test: CO & Architecture - Clock Frequency
I got 34 as answer, but given is 35.
I got 34 as answer, but given is 35.
rahul sharma 5
377
views
rahul sharma 5
asked
Nov 6, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
clock-frequency
+
–
2
votes
1
answer
14
MadeEasy Subject Test: Digital Logic - Flip Flop
For synchronous series counter of modulus 256, the propagation delay for each flip flop is 25 nsec and propagation delay of each two input AND gate is 5 nsec. What is the maximum frequency of MOD 256 counter ?(in MHz) a)18.18 b)19.18 c)20. ... makes Frequency = 1/(30 nsec) = 33.33 Mhz? please correct me where I am going wrong. Thanks for your help :)
For synchronous series counter of modulus 256, the propagation delay for each flip flop is 25 nsec and propagation delay of each two input AND gate is 5 nsec. What is the...
Kamal Pratap
502
views
Kamal Pratap
asked
Oct 10, 2017
Digital Logic
made-easy-test-series
digital-logic
synchronous-asynchronous-circuits
clock-frequency-flop
flip-flop
+
–
4
votes
1
answer
15
gatebook mt2
A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations. ADD Rs1, Rs2, Rd /* Add Rs1 to Rs2 and put the sum in Rd */ MUL Rs1, Rs2, Rd /* Multiply Rs1 by Rs2 and put the product in Rd */ An operation ... of clock cycles required for an operation sequence that computes the value of AB + ABC + BC ? (A) 5 (B) 6 (C) 7 (D) 8
A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations. ADD Rs1, Rs2, Rd /* Add Rs1 to Rs2 and put the ...
Purple
2.8k
views
Purple
asked
Feb 7, 2017
CO and Architecture
machine-instruction
co-and-architecture
clock-frequency
+
–
1
votes
1
answer
16
Whether to count MegaByte as 2^20 or 10^6
The first word of the memory block (each block contains 4 words of 4 bytes each) takes 5 clock cycles and remaining 3 words are transferred in consecutive cycles. Given the clock rate is 100 MHz. The data rate (in MBps) of memory for transferring one ... Please give me reference for that ! (So I can be happy :D ) From Made Easy FLT 6-Practice Test 14 Q 61
The first word of the memory block (each block contains 4 words of 4 bytes each) takes 5 clock cycles and remaining 3 words are transferred in consecutive cycles. Given t...
Akash Kanase
659
views
Akash Kanase
asked
Dec 1, 2015
CO and Architecture
co-and-architecture
clock-frequency
+
–
4
votes
2
answers
17
gatebook mt2 qn-36
Consider a simple in-order five-stage pipeline with a two-cycle branch misprediction penalty and a single-cycle load-use delay penalty. For a specific program, 30% of the instructions are loads, 20% are branches, the remaining 50% of instructions are ... dependent instruction, and 75% of branches are predicted correctly. What is the average CPI of this program on this processor?
Consider a simple in-order five-stage pipeline with a two-cycle branch misprediction penalty and a single-cycle load-use delay penalty. For a specific program, 30% of the...
Purple
1.8k
views
Purple
asked
Feb 7, 2017
CO and Architecture
co-and-architecture
machine-instruction
clock-frequency
+
–
0
votes
2
answers
18
Frequency of output signal?
I got the ans as 1/(5*25) = 1/125. None of the, match
I got the ans as 1/(5*25) = 1/125. None of the, match
prasitamukherjee
679
views
prasitamukherjee
asked
Dec 18, 2016
Digital Logic
digital-logic
clock-frequency
digital-counter
+
–
3
votes
1
answer
19
Test by Bikram | Mock GATE | Test 4 | Question: 51
In a synchronous series counter of Modulus $256$, the propagation delay for each $2$ input AND gate is $5$ ns and for each flip-flop is $25$ ns. The maximum frequency of the Mod-256 counter is _____MHz.
In a synchronous series counter of Modulus $256$, the propagation delay for each $2$ input AND gate is $5$ ns and for each flip-flop is $25$ ns. The maximum frequency of ...
Bikram
931
views
Bikram
asked
May 14, 2017
Digital Logic
tbb-mockgate-4
numerical-answers
digital-logic
clock-frequency
digital-counter
synchronous-asynchronous-circuits
+
–
7
votes
2
answers
20
Made Easy CA pipeline q2
A 5-stage pipeline is used to overlap all the instructions except the branch instructions. The target of the branch can't be fetched till the current instruction is completed. What is the throughout of the system if 20% of instructions are branch instructions ignore the ... of 4 cycles. A.55 MIPS B.45 MIPS C. 65 MIPS D. None of these. (explain the solution as well)
A 5-stage pipeline is used to overlap all the instructions except the branch instructions. The target of the branch can't be fetched till the current instruction is compl...
khushtak
3.2k
views
khushtak
asked
Oct 19, 2015
CO and Architecture
co-and-architecture
pipelining
clock-frequency
+
–
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