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Answers by Ram Swaroop
1
votes
1
UGC NET CSE | June 2019 | Part 2 | Question: 11
Which type of addressing mode, less number of memory references are required? Immediate Implied Register Indexed
Which type of addressing mode, less number of memory references are required?ImmediateImpliedRegisterIndexed
6.5k
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answered
Mar 11, 2020
CO and Architecture
ugcnetcse-june2019-paper2
co-and-architecture
addressing-modes
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–
0
votes
2
ISRO2020-15
A stack organized computer is characterised by instructions with indirect addressing direct addressing zero addressing index addressing
A stack organized computer is characterised by instructions withindirect addressingdirect addressingzero addressingindex addressing
4.4k
views
answered
Mar 11, 2020
CO and Architecture
isro-2020
co-and-architecture
addressing-modes
normal
+
–
2
votes
3
GATE CSE 2020 | Question: 19
A multiplexer is placed between a group of $32$ registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The number of select lines needed for the multiplexer is ______.
A multiplexer is placed between a group of $32$ registers and an accumulator to regulate data movement such that at any given point in time the content of only one regist...
6.8k
views
answered
Feb 12, 2020
Digital Logic
gatecse-2020
numerical-answers
digital-logic
multiplexer
1-mark
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–
1
votes
4
GATE CSE 2020 | Question: 18
Let $G$ be a group of $35$ elements. Then the largest possible size of a subgroup of $G$ other than $G$ itself is _______.
Let $G$ be a group of $35$ elements. Then the largest possible size of a subgroup of $G$ other than $G$ itself is _______.
9.4k
views
answered
Feb 12, 2020
Set Theory & Algebra
gatecse-2020
numerical-answers
group-theory
easy
1-mark
+
–
2
votes
5
GATE CSE 2020 | Question: 14
Which one of the following is used to represent the supporting many-one relationships of a weak entity set in an entity-relationship diagram? Diamonds with double/bold border Rectangles with double/bold border Ovals with double/bold border Ovals that contain underlined identifiers
Which one of the following is used to represent the supporting many-one relationships of a weak entity set in an entity-relationship diagram?Diamonds with double/bold bor...
13.3k
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answered
Feb 12, 2020
Databases
gatecse-2020
databases
er-diagram
1-mark
+
–
2
votes
6
GATE CSE 2020 | Question: GA-6
Goods and Services Tax (GST) is an indirect tax introduced in India in $2017$ that is imposed on the supply of goods and services, and it subsumes all indirect taxes except few. It is a destination-based tax imposed on goods and services used, ... indirect taxes. GST does not have a component specific to UT. GST is imposed at the point of usage of goods and services.
Goods and Services Tax (GST) is an indirect tax introduced in India in $2017$ that is imposed on the supply of goods and services, and it subsumes all indirect taxes exce...
3.3k
views
answered
Feb 12, 2020
Verbal Aptitude
gatecse-2020
verbal-aptitude
verbal-reasoning
passage-reading
2-marks
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2
votes
7
GATE CSE 2020 | Question: GA-4
The dawn of the $21$st century witnessed the melting glaciers oscillating between giving too much and too little to billions of people who depend on them for fresh water. The UN climate report estimates that without deep cuts to man- ... billions of people. Billions of people are responsible for man-made emissions. Billions of people are affected by melting glaciers.
The dawn of the $21$st century witnessed the melting glaciers oscillating between giving too much and too little to billions of people who depend on them for fresh water....
3.7k
views
answered
Feb 12, 2020
Verbal Aptitude
gatecse-2020
verbal-aptitude
verbal-reasoning
passage-reading
1-mark
+
–
10
votes
8
GATE CSE 2020 | Question: GA-2
His knowledge of the subject was excellent but his classroom performance was_______. extremely poor good desirable praiseworthy
His knowledge of the subject was excellent but his classroom performance was_______.extremely poorgooddesirablepraiseworthy
5.9k
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answered
Feb 12, 2020
Verbal Aptitude
gatecse-2020
verbal-aptitude
english-grammar
meaning
1-mark
+
–
0
votes
9
Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 24 (Page No. 256)
A machine has $48-bit$ virtual addresses and $32-bit$ physical addresses. Pages are $8\: KB.$ How many entries are needed for a single-level linear page table?
A machine has $48-bit$ virtual addresses and $32-bit$ physical addresses. Pages are $8\: KB.$ How many entries are needed for a single-level linear page table?
733
views
answered
Jan 29, 2020
Operating System
tanenbaum
operating-system
memory-management
paging
descriptive
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–
3
votes
10
MadeEasy Test Series: Compiler Design - Intermediate Code
a x b x c + d - a + e x f - g + h order of precedence : x>+>- ; with x is left associative and +, - as right. Min number of variables required in TAC? Should'nt the expression be expressed as : ((a x b) x c) + d - a + (e x f) - g + h (((a x b) x c) + (d - (a + (e x f)) - (g + h)))
a x b x c + d - a + e x f - g + horder of precedence : x>+>- ; with x is left associative and +, - as right.Min number of variables required in TAC?Should'nt the expressi...
1.1k
views
answered
Jan 24, 2020
Compiler Design
made-easy-test-series
compiler-design
intermediate-code
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–
0
votes
11
practice questions
we are given two strings: String S of length n and string T of length m for the LCS problem, we have produced the following exponential time recursive program. LCM (S, n, T, m) { if (n == 0||m == 0) return 0 if (S[n] == T[m]) result t = 1 + LCS ( ... (S, n, T, m - 1)); return result; } then the number of times that LCS (S, 1, T, 1) is recursively called equals ________ plz solve?
we are given two strings: String S of length n and string T of length m for theLCS problem, we have produced the following exponential time recursiveprogram.LCM (S, n, T,...
1.0k
views
answered
Jan 18, 2020
Algorithms
recursion
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–
9
votes
12
GATE CSE 2006 | Question: 37
Consider the circuit in the diagram. The $\oplus$ operator represents Ex-OR. The D flip-flops are initialized to zeroes (cleared). The following data: $100110000$ is supplied to the “data” terminal in nine clock cycles. After that the values of $q_{2}q_{1}q_{0}$ are: $000$ $001$ $010$ $101$
Consider the circuit in the diagram. The $\oplus$ operator represents Ex-OR. The D flip-flops are initialized to zeroes (cleared).The following data: $100110000$ is suppl...
16.0k
views
answered
Jan 8, 2020
Digital Logic
gatecse-2006
digital-logic
circuit-output
easy
+
–
5
votes
13
GATE CSE 1987 | Question: 1-IV
The output $F$ of the below multiplexer circuit can be represented by $AB+B\bar{C}+\bar{C}A+\bar{B}\bar{C}$ $A\oplus B\oplus C$ $A \oplus B$ $\bar{A} \bar{B} C+ \bar{A} B \bar{C}+A \bar{B} \bar{C}$
The output $F$ of the below multiplexer circuit can be represented by$AB+B\bar{C}+\bar{C}A+\bar{B}\bar{C}$$A\oplus B\oplus C$$A \oplus B$$\bar{A} \bar{B} C+ \bar{A} B \ba...
4.6k
views
answered
Jan 6, 2020
Digital Logic
gate1987
digital-logic
combinational-circuit
multiplexer
circuit-output
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–
0
votes
14
GATE Overflow | General Aptitude | Test 2 | Question: 7
Pick the word which fills the blank suitably The messages went $\_\_\_\_\_$ until a decision was made. back and forth deliberated discussed back
Pick the word which fills the blank suitablyThe messages went $\_\_\_\_\_$ until a decision was made.back and forthdeliberateddiscussedback
333
views
answered
Jan 5, 2020
Verbal Aptitude
go-general-aptitude-2
most-appropriate-word
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–
1
votes
15
UGC NET CSE | November 2017 | Part 3 | Question: 51
User level threads are threads that are visible to the programmer and are unknown to the kernel. The operating system kernel supports and manages kernel level threads. Three different types of models relate user and kernel level threads. Which of the following ... is false; (ii) is true Both (i) and (ii) are true Both (i) and (ii) are false
User level threads are threads that are visible to the programmer and are unknown to the kernel. The operating system kernel supports and manages kernel level threads. Th...
1.1k
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answered
Jan 4, 2020
Unknown Category
ugcnetcse-nov2017-paper3
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30
votes
16
GATE CSE 2015 Set 1 | Question: 55
The least number of temporary variables required to create a three-address code in static single assignment form for the expression $q + r / 3 + s - t * 5 + u * v/w$ is__________________.
The least number of temporary variables required to create a three-address code in static single assignment form for the expression $q + r / 3 + s - t * 5 + u * v/w$ is_...
29.4k
views
answered
Dec 1, 2019
Compiler Design
gatecse-2015-set1
compiler-design
intermediate-code
normal
numerical-answers
static-single-assignment
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–
0
votes
17
Ace Test Series 2019: DBMS - SQL Output
1.3k
views
answered
Nov 30, 2019
Databases
databases
sql
ace-test-series
+
–
0
votes
18
Discrete Mathematics Thegatebook
how many positive integers between 50 and 100, (a) divisible by 7 (b) divisible by 11 (c) divisible by 7 and 11?
how many positive integers between 50 and 100,(a) divisible by 7(b) divisible by 11(c) divisible by 7 and 11?
719
views
answered
Nov 10, 2019
Combinatory
inclusion-exclusion
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–
0
votes
19
UPPCL AE 2018:80
In a high school, a class teacher is scheduling the six subjects into periods $1$ through $6$ for her class. The subjects are: Hindi, English, Mathematics, Science, History and Geography. She has to abide by the following conditions: ... or immediately after Hindi If the Mathematics period is scheduled before Science, then Geography must be which period? second fourth third fifth
In a high school, a class teacher is scheduling the six subjects into periods $1$ through $6$ for her class. The subjects are: Hindi, English, Mathematics, Science, Histo...
338
views
answered
Oct 4, 2019
Analytical Aptitude
uppcl2018
analytical-aptitude
logical-reasoning
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–
3
votes
20
Q26 ch-5 M_E workbook
suppose that in 1000 memory reference there are 40 misses in the first level cache and 20 misses in the second level cache. Assume miss penalty from the L2 cache to memory is 100 cycles the hit time of the L2 cache is 10 clock cycles.the hit time of ... reference per instruction) x (miss rate) x (miss penalty) right?? so which miss rate and miss penalty should i put here?
suppose that in 1000 memory reference there are 40 misses in the first level cache and 20 misses in the second level cache. Assume miss penalty from the L2 cache to memor...
12.4k
views
answered
Aug 25, 2019
CO and Architecture
co-and-architecture
cache-memory
clock-frequency
clock-cycles
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–
0
votes
21
computer organization
suppose that in 1000 memory reference there are 40 misses in the first level cache and 20 misses in the second level cache. Assume miss penalty from the L2 cache to memory is 100 cycles the hit time of the L2 cache is 10 clock cycles.the hit time of the L1 cache is 1 clock cycle. what is average memory access time?
suppose that in 1000 memory reference there are 40 misses in the first level cache and 20 misses in the second level cache. Assume miss penalty from the L2 cache to memor...
1.4k
views
answered
Aug 25, 2019
0
votes
22
minimum number of registers
Consider the following expression and identify minimum number of registers required to implement the following expression : (a-b)+(e+(c-d))/f Can anyone please give the theory or notes of prerequisites -, how to solve these questions. The solution of the above ... adding R1 to the R2 and result is stored back into R1 since R1=R1+R2. Number of registers used is only 3.
Consider the following expression and identify minimum number of registers required to implement the following expression : (a-b)+(e+(c-d))/fCan anyone please give the th...
1.4k
views
answered
Aug 18, 2019
CO and Architecture
co-and-architecture
register-allocation
+
–
0
votes
23
MadeEasy Test Series 2018: Compiler Design - Runtime Environments
Consider the following statements: S1 : Static allocation can not support recursive function. S2 : Stack allocation can support pointers but can not deallocate storage at run-time. S3 : Heap allocation can support pointers and it can allocate or deallocate ... statements are true? a S1 and S2 b S2 and S3 c S3 and S1 d S1, S2 and S3
Consider the following statements:S1 : Static allocation can not support recursive function.S2 : Stack allocation can support pointers but can not deallocate storage at r...
3.1k
views
answered
Aug 18, 2019
Compiler Design
compiler-design
runtime-environment
made-easy-test-series
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–
0
votes
24
MadeEasy Test Series 2018: Compiler Design - Runtime Environments
Match the following with respect to activation record fields: A 1 → A, D; 2 → B, C B 1 → A, C; 2 → B, D C 1 → B, C; 2 → A, D D 1 → B, D; 2 → A, C Doubt:- Control link points to caller activation record.Can some one confirm?
Match the following with respect to activation record fields:A 1 → A, D; 2 → B, CB 1 → A, C; 2 → B, DC 1 → B, C; 2 → A, DD 1 → B, D; 2 → A, CDoubt:- Contr...
1.8k
views
answered
Aug 18, 2019
Compiler Design
compiler-design
runtime-environment
made-easy-test-series
+
–
2
votes
25
GATE CSE 2018 | Question: 37
A lexical analyzer uses the following patterns to recognize three tokens $T_1, T_2$, and $T_3$ over the alphabet $\{a, b, c\}$. $T_1: a?(b \mid c)^\ast a$ $T_2: b?(a \mid c)^\ast b$ ... the string $bbaacabc$ is processed by the analyzer, which one of the following is the sequence of tokens it outputs? $T_1T_2T_3$ $T_1T_1T_3$ $T_2T_1T_3$ $T_3T_3$
A lexical analyzer uses the following patterns to recognize three tokens $T_1, T_2$, and $T_3$ over the alphabet $\{a, b, c\}$.$T_1: a?(b \mid c)^\ast a$$T_2: b?(a \mid c...
21.6k
views
answered
Aug 15, 2019
Compiler Design
gatecse-2018
compiler-design
lexical-analysis
normal
2-marks
+
–
2
votes
26
MadeEasy Test Series: Compiler Design - Syntax Directed Translation
Question: Options:
Question:Options:
615
views
answered
Jul 29, 2019
Compiler Design
made-easy-test-series
compiler-design
syntax-directed-translation
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–
0
votes
27
compiler design, Syntax directed tree
Select the correct one from the below given options. 1. The parser’s output is abstract syntax tree, which represents the grammatical structure of the parse input. 2. Parse tree is condensed form of Abstract Syntax tree. 3. In abstract syntax tree the operators can appear as leaves while keywords cannot appear as leaves. 4.All of the above are true
Select the correct one from the below given options.1. The parser’s output is abstract syntax tree, which represents the grammatical structure of the parse input. 2. Pa...
591
views
answered
Jul 29, 2019
Compiler Design
compiler-design
syntax-directed-translation
syntax-directed-translation
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–
0
votes
28
Testbook Test Series: Compiler Design - Syntax Directed Translation
504
views
answered
Jul 29, 2019
Compiler Design
compiler-design
syntax-directed-translation
testbook-test-series
+
–
11
votes
29
GATE2019 EC: GA-7
The bar graph in panel (a) shows the proportion of male and female illiterates in $2001$ and $2011.$ The proportions of males and females in $2001$ and $2011$ are given in Panel (b) and (c), respectively. The total population did not change during this period. The percentage increase in the total number of literates from $2001$ to $2011$ is ______. $30.43$ $33.43$ $34.43$ $35.43$
The bar graph in panel (a) shows the proportion of male and female illiterates in $2001$ and $2011.$ The proportions of males and females in $2001$ and $2011$ are given i...
5.2k
views
answered
Jul 24, 2019
Quantitative Aptitude
gate2019-ec
quantitative-aptitude
data-interpretation
bar-graph
+
–
1
votes
30
Galvin Edition 9 Exercise 4 Question 12 (Page No. 192)
Using Amdahl’s Law, calculate the speedup gain of an application that has a 60 percent parallel component for (a) two processing cores and (b) four processing cores.
Using Amdahl’s Law, calculate the speedup gain of an application that has a 60 percent parallel component for (a) two processing cores and (b) four processing cores.
4.0k
views
answered
Jul 23, 2019
Operating System
galvin
operating-system
threads
descriptive
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