Consider the following program segment for a CPU having three Registers $R1, R2,$ and $R3$:
$$ \begin{array}{|l|l|l|} \hline \text{Instruction} & \text{Operation} & \text{Instruction } \\ {} & {} & \text{Size In words} \\ \hline \text{MOV R1,200} & R1\leftarrow[200] & 2 \\ \hline \text{ADD R2,R1} & R2\leftarrow R2 + R1 & 1 \\ \hline \text{MUL R3,R1} & R3\leftarrow R3 \:\ast R1 & 1 \\ \hline \text{MOV 200,R3} & M[200]\leftarrow R3 & 2 \\ \hline \text{HALT} & \text{Machine Halts} & 1 \\ \hline \end{array}$$
The memory is byte-addressable with word size $2 Bytes$, and the program is loaded starting from memory location $200$. If an interruption occurs while the ‘Multiply’ instruction is being executing by the CPU, then the return address saved onto the stack will be _______.