edited by
405 views
1 votes
1 votes
Consider the following program segment for a CPU having three Registers $R1, R2,$ and $R3$:

$$ \begin{array}{|l|l|l|} \hline \text{Instruction} & \text{Operation} & \text{Instruction } \\ {} & {} & \text{Size In words} \\ \hline \text{MOV R1,200} & R1\leftarrow[200] & 2 \\ \hline \text{ADD R2,R1} & R2\leftarrow R2 + R1 & 1  \\ \hline \text{MUL R3,R1} & R3\leftarrow R3 \:\ast R1 & 1 \\ \hline \text{MOV 200,R3} & M[200]\leftarrow R3 & 2  \\ \hline \text{HALT} & \text{Machine Halts} & 1 \\ \hline \end{array}$$

The memory is byte-addressable with word size $2 Bytes$, and the program is loaded starting from memory location $200$. If an interruption occurs while the ‘Multiply’ instruction is being executing by the CPU, then the return address saved onto the stack will be _______.
edited by

3 Answers

Best answer
5 votes
5 votes
1st Instruction requires 2 *16 bit = 4 byte
2nd instruction requires 1 *16 = 2 byte
3rd instruction requires  1* 16 = 2 bytes
So 1st  Instruction  goes from 200 to  203 address/ memory location
 2nd instruction goes from 204 to 205 memory location
3rd instruction goes from  206 to 207  memory location
So the starting address of 4th instruction  208 will be stored on the top of the stack.
selected by
2 votes
2 votes
     __________
200 |          |
201 |   MOV    |
202 |          |
203 |__________|
204 |   ADD    |
205 |__________|
206 |   MUL    |
207 |__________|
208 |   ...    |
. 
.

Program will be saved in memory like this. Each word is 2 bytes long, and each instruction takes either 1 word or 2 word as given in the table. And the memory is byte addressable, so every byte should be given separate addresses.

Whenever an interrupt occurs during an instruction, that instruction is completed and then the interrupt is addressed.

So, the return address is 208, i.e. next instruction after MUL.

0 votes
0 votes

The memory is byte-addressable

So contents of PC are in Bytes.

While executing MUL at 206th Byte, PC points to next instruction, ie at 208th Byte. (Answer)


When the interrupt occurs, the Program Status Word, along with contents of PC is saved onto the stack.

Answer:

Related questions

308
views
1 answers
1 votes
Bikram asked Nov 25, 2016
308 views
Consider two pipelines A and B. Pipeline A has $8$ stages with uniform stage delay of $2$ns. Pipeline B has $5$ stages with uniform stage delays of $3$ns. Time saved (in ...
1.2k
views
2 answers
3 votes
Bikram asked Nov 25, 2016
1,231 views
A hard disk is connected to a $2$ GHz processor through a DMA controller which works in burst mode. The initial set up of a DMA transfer takes $1000$ clock cycles for the...
467
views
3 answers
1 votes
Bikram asked Nov 25, 2016
467 views
Consider a hypothetical processor that supports two addresses one address and zero address instructions. It has a $256$ word memory, and a $20$ bit instruction is place...
2.0k
views
2 answers
2 votes
Bikram asked Nov 25, 2016
1,955 views
In a computer system, there are $5$ registers, namely $PC, AR, DR, IR,$ and $SC$. The initial content of $PC$ is $7FF$. The content of memory at address $7FF$ is $EA9F$...