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A Simple Illustration
Cache Memory
Recent questions tagged cache-memory
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301
self doubt write back cache
https://gateoverflow.in/35154/write-back-and-write-through every thing is clear but a doubt is tht why only the case of dirty bit is considered ...and why the case of clean bit is left while solving ??? and when to take both cases??should be explicitly mentioned in the question??
https://gateoverflow.in/35154/write-back-and-write-through every thing is clear but a doubt is tht why only the case of dirty bit is considered ...and why the case of cle...
eyeamgj
176
views
eyeamgj
asked
Sep 15, 2018
CO and Architecture
co-and-architecture
cache-memory
write-back
self-doubt
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0
votes
1
answer
302
Cache
What happens on write miss in a write back cache? First write in main memory then bring the block to cache (dirty bit = 0) or First bring the block to cache then write it (dirty bit = 1).
What happens on write miss in a write back cache?First write in main memory then bring the block to cache (dirty bit = 0) orFirst bring the block to cache then write it (...
MayankSharma
854
views
MayankSharma
asked
Sep 14, 2018
CO and Architecture
co-and-architecture
cache-memory
general-topic-doubt
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0
votes
0
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303
CO general doubt
Consider an array has 100 elements and each element occupies 4 words .A 32 word cache is used and divided into a block of 8 words .What is the hit ratio for this statement for(i=0; i<100; i++) A[i] = A[i]+10; I just want to ask that whenever ... ie 2 elements) are fetched and placed in cache,so why we are doing like this is it because we have to follow law of spatial locality ?
Consider an array has 100 elements and each element occupies 4 words .A 32 word cache is used and divided into a block of 8 words .What is the hit ratio for this stateme...
Prince Sindhiya
407
views
Prince Sindhiya
asked
Sep 14, 2018
CO and Architecture
co-and-architecture
memory-interfacing
array
cache-memory
general-topic-doubt
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0
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0
answers
304
selfdoubt
https://gateoverflow.in/2078/gate2014-3-44 in this question the reason of dividing is that frequenies of operations are given in quantity not in percentage???
https://gateoverflow.in/2078/gate2014-3-44in this question the reason of dividing is that frequenies of operations are given in quantity not in percentage???
eyeamgj
139
views
eyeamgj
asked
Sep 13, 2018
CO and Architecture
co-and-architecture
cache-memory
self-doubt
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0
votes
0
answers
305
Computer organisation- DMA
sidlewis
231
views
sidlewis
asked
Sep 12, 2018
CO and Architecture
co-and-architecture
cache-memory
array
clock-cycles
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0
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0
answers
306
Computer Organisation- Cache
sidlewis
277
views
sidlewis
asked
Sep 12, 2018
CO and Architecture
co-and-architecture
cache-memory
numerical-answers
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0
votes
0
answers
307
Set Associative cache. Calculate cache capacity.
Consider a 4 - way set associative cache with 'L' blocks of 16 words each. Cache block is associated with dirty bit field and valid bit field. Calculate cache capacity with a word size of 2 bytes and tag size of 22 bits.
Consider a 4 - way set associative cache with 'L' blocks of 16 words each. Cache block is associated with dirty bit field and valid bit field. Calculate cache capacity wi...
Mk Utkarsh
1.0k
views
Mk Utkarsh
asked
Sep 12, 2018
CO and Architecture
cache-memory
co-and-architecture
numerical-answers
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3
votes
2
answers
308
#Cache
Consider a direct map cache of 8 words, with block 2 words per Block. The following sequence of access to memory block 0,5,2,7,4,0 and 4 is repeated 10 times. Q1) number of compulsory miss? Q2) number of conflict misses? Q3) The number of capacity misses?
Consider a direct map cache of 8 words, with block 2 words per Block. The following sequence of access to memory block 0,5,2,7,4,0 and 4 is repeated 10 times.Q1) number o...
Ayan21
1.0k
views
Ayan21
asked
Sep 11, 2018
CO and Architecture
co-and-architecture
cache-memory
misses
numerical-answers
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0
votes
0
answers
309
CACHE SELF DOUBT 2
Balaji Jegan
184
views
Balaji Jegan
asked
Sep 10, 2018
CO and Architecture
co-and-architecture
cache-memory
write-through
numerical-answers
self-doubt
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0
votes
0
answers
310
CACHE SELF DOUBT 1
Balaji Jegan
279
views
Balaji Jegan
asked
Sep 10, 2018
CO and Architecture
co-and-architecture
cache-memory
numerical-answers
write-back
self-doubt
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0
votes
0
answers
311
Dout Write_back
IN write-back policies what does meant by the update in memory is supposed to happen when block in cache is evicted?
IN write-back policies what does meant by the update in memory is supposed to happen when block in cache is evicted?
anonymous
244
views
anonymous
asked
Sep 10, 2018
CO and Architecture
co-and-architecture
cache-memory
write-back
self-doubt
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0
votes
1
answer
312
Self doubt
What is the difference between Memory access time and Memory latency. Memory access time : It is the time elapsed between CPU generating request for particular address and the time it locates it on Memory before actual transfer of bytes into registers. Is Memory Latency is same as Memory access time ???
What is the difference between Memory access time and Memory latency.Memory access time : It is the time elapsed between CPU generating request for particular address and...
jatin khachane 1
183
views
jatin khachane 1
asked
Sep 9, 2018
CO and Architecture
co-and-architecture
cache-memory
self-doubt
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0
votes
0
answers
313
cache memory(direct mapped)
After time slot 40;00 there is a question related to direct mapped cache in which there is 32 bit of data and cpu generates 32 bit address and memory is byte addressable.how many total bits are require for tag bit for a cache having 64 KB of data .i am confused with solution .what is page size??can anyone explain???
After time slot 40;00 there is a question related to direct mapped cache in which there is 32 bit of data and cpu generates 32 bit address and memory is byte addressable...
BASANT KUMAR
342
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BASANT KUMAR
asked
Sep 8, 2018
CO and Architecture
co-and-architecture
cache-memory
self-doubt
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0
votes
1
answer
314
Cache
Shivangi Parashar 2
594
views
Shivangi Parashar 2
asked
Sep 6, 2018
CO and Architecture
cache-memory
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1
votes
0
answers
315
Cache-tag-directory
What is the size of tag in cache directory for direct and set-associative memory? For set-associative memory do we multiply by no of sets or no of blocks? According to me Size of Tag in cache directory = Number of tag bits(+ any extra bits like valid, ... = Number of tag bits(+ any extra bits like valid, modified etc) * number of sets Tag is associated with each block or set?
What is the size of tag in cache directory for direct and set-associative memory?For set-associative memory do we multiply by no of sets or no of blocks?According to meSi...
Apoorva Jain
1.4k
views
Apoorva Jain
asked
Sep 2, 2018
CO and Architecture
cache-memory
co-and-architecture
direct-mapping
set-associative-mapping
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1
votes
1
answer
316
Miss latency and miss penalty
Are miss latency & miss penalty same in cache?if no then what's the difference???
Are miss latency & miss penalty same in cache?if no then what's the difference???
MayankSharma
2.5k
views
MayankSharma
asked
Aug 29, 2018
CO and Architecture
co-and-architecture
cache-memory
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2
votes
1
answer
317
MadeEasy Test Series Tag,Set and Word field
Consider a computer system has a main memory consisting of 1M 16 bit words. It also has a 4 K-word cache organized in the block set associative manner, with 4 blocks per set and 64 words per block. What is the number of bits in each of the TAG, SET and WORD field of main memory address format 11, 4, 6 10, 5, 6 10, 4, 7 11, 4, 7
Consider a computer system has a main memory consisting of 1M 16 bit words. It also has a 4 K-word cache organized in the block set associative manner, with 4 blocks per ...
Mk Utkarsh
7.7k
views
Mk Utkarsh
asked
Aug 23, 2018
CO and Architecture
cache-memory
co-and-architecture
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0
votes
2
answers
318
MadeEasy Test Series: CO & Architecture - Cache Memory
Consider a memory access to main memory on a cache miss takes 100 ns and memory access to cache at cache hit takes 10 ns. If 75% processors memory request results in cache hit the average memory access time is _____ ns.
Consider a memory access to main memory on a cache miss takes 100 ns and memory access to cache at cache hit takes 10 ns. If 75% processors memory request results in cach...
Mk Utkarsh
1.5k
views
Mk Utkarsh
asked
Aug 23, 2018
CO and Architecture
co-and-architecture
made-easy-test-series
cache-memory
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1
votes
2
answers
319
Two level of cache
Consider a two level cache system. For 100 memory references 20 misses in 1st level cache,10 misses in second level cache. Miss penalty from second level to memory is 40 cycles. if Total average = 7.6 cycles, then hit time of second level cache ? Assume hit time of second level cache is two times the first level cache? Ans. 4
Consider a two level cache system. For 100 memory references 20 misses in 1st level cache,10 misses in second level cache. Miss penalty from second level to memory is 40 ...
Na462
5.7k
views
Na462
asked
Aug 16, 2018
CO and Architecture
co-and-architecture
cache-memory
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0
votes
1
answer
320
Explain this. And explain mapping. Just confuse between words per block. Per word n etc
Aman mourya
273
views
Aman mourya
asked
Aug 15, 2018
CO and Architecture
cache-memory
co-and-architecture
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–
0
votes
1
answer
321
Cache Capacity
if in a question it ask for cache capacity the is it calculated by follwing... cache capacity=cache size+ tag memory size+dirty bit cache capacity=tag bits * no. of cache lines which one is correct?
if in a question it ask for cache capacity the is it calculated by follwing...cache capacity=cache size+ tag memory size+dirty bitcache capacity=tag bits * no. of cache l...
Nihar Ranjan Panda
510
views
Nihar Ranjan Panda
asked
Aug 6, 2018
CO and Architecture
cache-capacity
cache-memory
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0
votes
1
answer
322
Multilevel Cache Access time
Ans. A
Ans. A
Na462
1.6k
views
Na462
asked
Aug 6, 2018
CO and Architecture
co-and-architecture
cache-memory
memory-management
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–
1
votes
1
answer
323
performance of cache memory
in cache performace i have confusion about where to use which formula like for write through whether use H (tc) + (1-H) (tc+m) or H (tc) + (1-H) (m) and how to identify whether cache memory is hierarchical or not from question can anyone give me all formula related to cache performance with explanation
in cache performace i have confusion about where to use which formula likefor write through whether use H (tc) + (1-H) (tc+m) or H (tc) + (1-H) (m)and how to identify wh...
Rahul_Rathod_
616
views
Rahul_Rathod_
asked
Aug 6, 2018
CO and Architecture
cache-memory
co-and-architecture
multilevel-cache
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–
0
votes
0
answers
324
Direct Map Cache
Ans. 1
Ans. 1
Na462
618
views
Na462
asked
Aug 4, 2018
CO and Architecture
co-and-architecture
cache-memory
direct-mapping
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–
0
votes
0
answers
325
Cache GATE Doubt
In the following question if we consider for various data types such as char,float and int how would the answer vary? https://gateoverflow.in/1442/gate2013-20
In the following question if we consider for various data types such as char,float and int how would the answer vary?https://gateoverflow.in/1442/gate2013-20
Devshree Dubey
574
views
Devshree Dubey
asked
Aug 3, 2018
CO and Architecture
co-and-architecture
cache-memory
+
–
0
votes
0
answers
326
performance cache exercise help
First level data cache: Direct mapping , writeThrough/write allocate , 8kb data and lines of 8 bytes, miss rate= 17% First level instructions cache: Direct mapping,, 4kb data and lines of 8 bytes, miss rate= 2% Second level unified cache: ... accesses to data memory and instructions of the total number of accesses? 5)What is the average memory access time? Thanks !!
First level data cache: Direct mapping , writeThrough/write allocate , 8kb data and lines of 8 bytes, miss rate= 17%First level instructions cache: Direct mapping,, 4kb d...
mauro5991
409
views
mauro5991
asked
Aug 2, 2018
CO and Architecture
virtual-memory
cache-memory
co-and-architecture
memory-management
multilevel-cache
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–
0
votes
0
answers
327
Cache Doubt
How does cache mapping of various type solve the problem of fragmentation?
How does cache mapping of various type solve the problem of fragmentation?
Devshree Dubey
164
views
Devshree Dubey
asked
Aug 2, 2018
CO and Architecture
co-and-architecture
cache-memory
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–
0
votes
0
answers
328
Cache Hits and Misses
Balaji Jegan
214
views
Balaji Jegan
asked
Aug 2, 2018
CO and Architecture
co-and-architecture
cache-memory
+
–
1
votes
0
answers
329
Memory Access Time
What is the difference between Effective Memory Access Time and Average Memory Access Time. Please tell in the context of both Hierarchical access as well as Simultaneous access.
What is the difference between Effective Memory Access Time and Average Memory Access Time. Please tell in the context of both Hierarchical access as well as Simultaneous...
Balaji Jegan
188
views
Balaji Jegan
asked
Aug 2, 2018
CO and Architecture
cache-memory
co-and-architecture
+
–
1
votes
1
answer
330
Locality of reference
How does the various types of locality of reference affects the cache access?
How does the various types of locality of reference affects the cache access?
Devshree Dubey
641
views
Devshree Dubey
asked
Aug 2, 2018
CO and Architecture
co-and-architecture
cache-memory
+
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