Recent questions tagged cache-memory / GATE Overflow for GATE CSE

45 votes

9 answers

361

GATE CSE 2018 | Question: 34
The size of the physical address space of a processor is $2^P$ bytes. The word length is $2^W$ bytes. The capacity of cache memory is $2^N$ bytes. The size of each cache block is $2^M$ words. For a $K$-way set-associative cache memory, the length (in number of bits) of the tag field is $P-N- \log_2K$ $P-N+ \log_2 K$ $P-N-M-W- \log_2 K$ $P-N-M-W+ \log_2 K$

The size of the physical address space of a processor is $2^P$ bytes. The word length is $2^W$ bytes. The capacity of cache memory is $2^N$ bytes. The size of each cache ...

gatecse

12.5k views

gatecse asked Feb 14, 2018

0 votes

1 answer

362

MadeEasy Test Series: CO & Architecture - Cache Memory
Assume that for a certain processor, main memory access time is 100 nanoseconds and cache memory access time is 20 nanoseconds. Suppose while running a program, it was observed that 25% of the processor’s requests result in a cache miss. What is the average access time in nanoseconds? A) 75 B) 80 C) 40 D) 45

Assume that for a certain processor, main memory access time is 100 nanoseconds and cache memory access time is 20 nanoseconds. Suppose while running a program, it was ob...

khedkar devidas

289 views

khedkar devidas asked Jan 30, 2018

1 votes

0 answers

363

MadeEasy Test Series: CO & Architecture - Addressing Modes
A computer has 256 KB, 8 way set associative write back data cache with block size 16 bytes. The processor send 36 bit addresses to the cache controller. Each tag directory entry contains, in addition to tag address, 1 valid bit and 1 matching bit. The size of ... above till here: TAG Size = $23\ bits * 2^{14}$ = $3\ bytes * 2^{14}$ = 48 KB

A computer has 256 KB, 8 way set associative write back data cache with block size 16 bytes. The processor send 36 bit addresses to the cache controller. Each tag directo...

Rishabh Gupta 2

1.0k views

Rishabh Gupta 2 asked Jan 30, 2018

0 votes

0 answers

364

Cache

Pawan Kumar 2

248 views

Pawan Kumar 2 asked Jan 29, 2018

1 votes

1 answer

365

Memory Organization
Q.1 What is diffrence between EMAT(effective) and AMAT(average mem access time)? Q.2 Suppose we have L1 cache ,L2cache and MM , and H1,M1, T1: hit/miss ratio, access time of L1 cache. And H2 , M2, T2 hit/miss ration of L2. amd MM access time is t3. Then how to calculate EMAT and AMAT?

Q.1 What is diffrence between EMAT(effective) and AMAT(average mem access time)?Q.2 Suppose we have L1 cache ,L2cache and MM , and H1,M1, T1: hit/miss ratio, access time ...

Prateek K

389 views

Prateek K asked Jan 29, 2018

1 votes

0 answers

366

Ace Test Series: CO & Architecture - Cache Memory Tag

Manis

393 views

Manis asked Jan 28, 2018

2 votes

1 answer

367

Ace test series: CO & Architecture - Cache Memory Tag

ashish pal

456 views

ashish pal asked Jan 28, 2018

7 votes

1 answer

368

Cache memory - Find Cache size ( given K, line size, tag memory, physical address space )
Consider a physically tagged, word addressable, 16-way set associative cache with the line size of 128 Bytes. What is the size of cache if tag memory size is 2Kbits. Further assume that physical address space is 24 bits and word size is 4 Bytes. a. 1 KB b. 2 KB c. 3 KB d. 4 KB

Consider a physically tagged, word addressable, 16-way set associative cache with the line size of 128 Bytes. What is the size of cache if tag memory size is 2Kbits. Furt...

Tuhin Dutta

1.9k views

Tuhin Dutta asked Jan 27, 2018

1 votes

0 answers

369

TEST SERIES CO

Ismail

249 views

Ismail asked Jan 27, 2018

2 votes

0 answers

370

MadeEasy Test Series 2018: CO & Architecture - Cache Memory
Answer given is 3. But I think the answer should be 4 conflict miss will occur in 100,108,114,1C7,128,1B5,100,108,1C7 (highlighted misses) My approach: I found that no. of sets is 2 and only 1 bit will be sufficient. ... areas. Need your help if I am doing wrong somewhere or may be answer is incorrect. Thanks in advance for your help.

Answer given is 3. But I think the answer should be 4 conflict miss will occur in 100,108,114,1C7,128,1B5,100,108,1C7 (highlighted misses)My approach: I found that no. o...

nishitshah

349 views

nishitshah asked Jan 26, 2018

1 votes

0 answers

371

Cache
What is Virtually Indexed Virtually Tagged (VIVT)? Similarly we have VIPT, PIPT, PIVT (P is physical) Short explanation or reference pls :)

What is Virtually Indexed Virtually Tagged (VIVT)?Similarly we have VIPT, PIPT, PIVT (P is physical)Short explanation or reference pls :)

gauravkc

284 views

gauravkc asked Jan 25, 2018

3 votes

1 answer

372

Cache Average access time
So as we know there are 2 different approaches for cache.. Sequential and the Hierarchical. Exactly which formula should I use when only access times and hit ratio is mentioned in case of 2 level memory system..? It would be great if someone explains how to approach questions related to average access time.

So as we know there are 2 different approaches for cache..Sequential and the Hierarchical. Exactly which formula should I use when only access times and hit ratio is ment...

Abhijit Howal

682 views

Abhijit Howal asked Jan 22, 2018

1 votes

1 answer

373

Ace Test Series: CO & Architecture - Cache Memory Tag
The answer was given as 22 bits. I didn't get their method of solving this question. Kindly explain the solution. I even doubt their answer.

The answer was given as 22 bits. I didn't get their method of solving this question. Kindly explain the solution. I even doubt their answer.

Asim Abbas

351 views

Asim Abbas asked Jan 22, 2018

2 votes

0 answers

374

cache
32-19=13=2^13bits=2^10B=1024? what is wrong with this?

32-19=13=2^13bits=2^10B=1024? what is wrong with this?

Inspiron

528 views

Inspiron asked Jan 21, 2018

3 votes

2 answers

375

#Conflict Misses
A byte addressable computer has a small data cache capable of holding 16 32-bit words. Each cache block consist of four 32 bits words. For the following sequence of main memory addresses (in hexadecimal). The conflict miss if 2-way set associative LRU cache is used is ________. 100, 108, 114, 1C7, 128, 1B5, 100, 108, 1C7

A byte addressable computer has a small data cache capable of holding 16 32-bit words. Each cache block consist of four 32 bits words. For the following sequence of main ...

VS

1.1k views

VS asked Jan 20, 2018

4 votes

1 answer

376

Gateforum Test Series

Sumaiya23

603 views

Sumaiya23 asked Jan 20, 2018

1 votes

1 answer

377

Memory access time
Suppose the time taken to write in cache is tc and time to write in main memory is tm. If write back policy is used, only the main memory is written and time taken is tm. But if write through is used, are the main memory and cache updated simultaneously (time taken would be tm) or serially (time taken would be tc + tm)?

Suppose the time taken to write in cache is tc and time to write in main memory is tm. If write back policy is used, only the main memory is written and time taken is tm....

Sumaiya23

728 views

Sumaiya23 asked Jan 18, 2018

3 votes

1 answer

378

Cache Memory
Consider the following statements: S1 : If capacity misses are most common then the designer should increase the cache associatively, in order to provide more flexibility when collision occurs. S2 : To hold the inclusion, lower level cache will be write through. Which of the statements are correct?

Consider the following statements:S1 : If capacity misses are most common then the designer should increase the cache associatively, in order to provide more flexibility ...

Harsh Mehta

751 views

Harsh Mehta asked Jan 16, 2018

3 votes

0 answers

379

Writeback formula doubt
In writeback cache, formula for write is given as ... $T_{memory\_block}$= Bring the block containing updated word to cache . Please help me .

In writeback cache, formula for write is given as$T_{write} = H \times T_{cache} + (1-H) \times (T_{cache} + T_{memory\_block} + T_{write\_back}) \\ \\ \text{ where } T_{...

Rajesh R

266 views

Rajesh R asked Jan 15, 2018

3 votes

1 answer

380

Virtual GATE question

Balaji Jegan

500 views

Balaji Jegan asked Jan 15, 2018

1 votes

0 answers

381

MadeEasy Test Series 2018: CO & Architecture - Cache Memory
A computer has a 256 KB, K-way set associative write-back data cache with block size of 32 B. The address sent to the cache controller by the processor is of 32 bits. In addition to the address tag, each cache tag directory contains 2 valid bits ... are used to address tag. What is the minimum value of K? A) 6 B) 5 C) 4 D) None of these

A computer has a 256 KB, K-way set associative write-back data cache with block size of 32 B. The address sent to the cache controller by the processor is of 32 bits. In ...

Prabhat Kumar Sing 1

377 views

Prabhat Kumar Sing 1 asked Jan 13, 2018

2 votes

1 answer

382

conflict miss
Can someone tell me the text-book definition for conflict miss?

Can someone tell me the text-book definition for conflict miss?

Warlock lord

1.7k views

Warlock lord asked Jan 12, 2018

4 votes

1 answer

383

average memory access time
The access time of cache memory is 45 nsec and that of main memory is 750 nsec. It is found that 75% of memory requests are for read and remaining for write. If the hit access for read is 0.9 and hit ratio for write is 1 and write through protocol is used, then the average memory access time is ________.

The access time of cache memory is 45 nsec and that of main memory is 750 nsec. It is found that 75% of memory requests are for read and remaining for write. If the hit a...

Jaspreet Kaur Bains

5.0k views

Jaspreet Kaur Bains asked Jan 11, 2018

4 votes

0 answers

384

CO: Memory

thepeeyoosh

534 views

thepeeyoosh asked Jan 11, 2018

2 votes

0 answers

385

CO: Cache Memory

thepeeyoosh

492 views

thepeeyoosh asked Jan 11, 2018

1 votes

0 answers

386

hierarchical accessing of blocks
Consider a hierarchical access of blocks for a multilevel cache. As per my understanding, in an Hierarchical accessing there is no search time for the cache calculated. When there is a miss, the memory access time and the cache access time is ... -isro2016-77 The question above should be clearly hierarchical. If I'm mistaken, please feel free to prove me wrong.

Consider a hierarchical access of blocks for a multilevel cache. As per my understanding, in an Hierarchical accessing there is no search time for the cache calculated. W...

Warlock lord

156 views

Warlock lord asked Jan 10, 2018

1 votes

0 answers

387

Memory levels
Suppose we have a 3 level memory hierarchy with following specs, level1 - 4 words per block, 4 blocks, the access time of 10ns/word. level2 - 16 words per block, 8 blocks, the access time of 20 ns/word. level3 - 32 words per block, 16 blocks, the access time ... when miss in l2 , it goes to l3, then a word will be read from level1. What is average access time for the above transfer?

Suppose we have a 3 level memory hierarchy with following specs,level1 - 4 words per block, 4 blocks, the access time of 10ns/word.level2 - 16 words per block, 8 blocks, ...

AnilGoudar

520 views

AnilGoudar asked Jan 10, 2018

4 votes

1 answer

388

MadeEasy Test Series 2018: CO & Architecture - Cache Memory
Consider a 16-way set associative cache which holds 64 KB of data. The size of physical address is of 40 bits. A cache block consist of 4 words. Every data word is of 32 bits. Assuming that all cache entries are ... (in hexadecimal) are supplied to the cache in the sequence given below : The number of compulsory misses are ________.

Consider a 16-way set associative cache which holds 64 KB of data. The size of physical address is of 40 bits. A cache block consist of 4 words. Every data word is of 32 ...

Saikat Dutta

883 views

Saikat Dutta asked Jan 10, 2018

3 votes

1 answer

389

MadeEasy Test Series 2018: CO & Architecture - Cache Memory
The designers of a cache system need to reduce the number of cache misses that occur in a certain group of programs. S1 : If compulsory misses are most common, then the designers should consider increasing the ... associativity, in order to provide more flexibility when a collision occurs. The number of statements are true __________.

The designers of a cache system need to reduce the number of cache misses that occur in a certain group of programs.S1 : If compulsory misses are most common, then the de...

Rajnish Kumar 1

578 views

Rajnish Kumar 1 asked Jan 10, 2018

3 votes

2 answers

390

Average Number of stalls
Consider a CPU contains 2000 instructions, there are 80 misses in the L1 cache and 40 misses in the L2 cache. Assume miss penalty from the L2 cache to memory is 200 clock cycles, the hit time of L2 cache is 30 clock cycles, the hit time of L1 cache is 5 clock cycles and ... 0.95 * 0 {As there is no stalls when hit in L1 cache} + 0.05(30 + 0.5 * 200) 6.5 stalls/instruction.

Consider a CPU contains 2000 instructions, there are 80 misses in the L1 cache and 40 misses in the L2 cache. Assume miss penalty from the L2 cache to memory is 200 cloc...

Shubhanshu

1.5k views

Shubhanshu asked Jan 7, 2018

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true

Slides