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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

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Highest voted questions in CO and Architecture

20 votes
2 answers
182
COA DMA doubt
What is formula for % of time CPU gets blocked?? Is it X(X+Y) or X/Y only??? What is formula for % of time CPU is consumed in Interuppt driven IO??? Formula for % of CPU slow down in interrupt driven IO???
What is formula for % of time CPU gets blocked??Is it X(X+Y) or X/Y only???What is formula for % of time CPU is consumed in Interuppt driven IO??? Formula for % of CPU s...
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19 votes
4 answers
186
GATE CSE 1990 | Question: 4-ii
State whether the following statements are TRUE or FALSE with reason: The data transfer between memory and I/O devices using programmed I/O is faster than interrupt-driven I/O.
State whether the following statements are TRUE or FALSE with reason:The data transfer between memory and I/O devices using programmed I/O is faster than interrupt-driven...
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19 votes
2 answers
190
GATE CSE 1992 | Question: 01-iii
Many microprocessors have a specified lower limit on clock frequency (apart from the maximum clock frequency limit) because _____
Many microprocessors have a specified lower limit on clock frequency (apart from the maximum clock frequency limit) because _____
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18 votes
1 answer
194
% time of CPU blocked in DMA
Please Explain the formulae for % time of CPU blocked in both Cycle Stealing mode and Burst mode of DMA
Please Explain the formulae for % time of CPU blocked in both Cycle Stealing mode and Burst mode of DMA
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18 votes
2 answers
195
pipeline_hazard
no of RAW,WAR and WAW ?
no of RAW,WAR and WAW ?
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17 votes
1 answer
197
Operand forwarding in pipeline
A $5$ stage pipelined processor has the following stages: $IF$ : instruction fetch $ID$ : instruction decode $EX$ : execute $MA$ : memory access $WB$ ... No. of cycles needed to execute these instructions using operand forwarding?
A $5$ stage pipelined processor has the following stages:$IF$ : instruction fetch$ID$ : instruction decode$EX$ : execute$MA$ : memory access$WB$ : write back$$\large\colo...
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