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Consider a computer having L1- data cache and main memory. The latencies of different kind accesses are as follows; cache hit 1-cycle; cache miss, 105 cycles; main memory access with cache disabled, 100 cycles. When you run a program with an overall miss rate of 5%, what will be the average memory access time(in CPU cycles)
in CO and Architecture by (51 points) | 56 views
6.2 ???
yes , ans is 6.2
0.95*1 + 0.05*105 = 6.2

main memory access with cache disabled, 100 cycles

Why it is written here.

Since miss in cache implicit means accessing main memory only.

In case of miss why you are not adding 100 cycles for accessing main memory
because it is already included in 105 cycles

1 Answer

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Best answer
We have given that cache hit then 1 cycle

which we can say (not always) that cache access time is 1 cycle

Now if there is cache hit or cache miss 1 cycle is required to search cache.

cache miss =105 cycle means 1 cycle for cache access + 100 cycles for main memory access + 4 cycle other overhead


If cache miss cycle was not given then T avg = 0.95*1+0.05*101 = 6 cycles

But we are given cache miss time T avg = 0.95*1+0.05*105= 6.2 cycles

This is my interpretation of this question
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