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Recent questions and answers in Digital Logic

1 vote
1 answer
1
The total number of comparisons performed in a 8-bit magnitude comparator consist of inputs A[A4, A3, A2, A1] and B[B4, B3, B2, B1] then condition for A>B is : A 255 x 26 B 255 x 27 C 255 x 28​​​​​ D 255 x 29
answered 1 day ago in Digital Logic vipin.gautam1906 169 views
0 votes
1 answer
2
The period of a signal is $100$ ms, then the frequency of this signal in kilohertz is ______ $10$ $10^{-1}$ $10^{-2}$ $10^{-3}$
answered Nov 23 in Digital Logic Sanjay Sharma 29 views
0 votes
1 answer
3
Simplified expression/s for following Boolean function $F(A,B,C,D)=\Sigma(0,1,2,3,6,12,13,14,15)$ is/are $A’B’+AB+A’C’D’$ $A’B’+AB+A’CD’$ $A’B’+AB+BC’D’$ $A’B’+AB+BCD’$ Choose the correct answer from the options given below: $(a)$ only $(b)$ only $(a)$ and $(b)$ only $(b)$ and $(d)$ only
answered Nov 22 in Digital Logic Sanjay Sharma 29 views
83 votes
17 answers
4
We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this counter is _____________.
answered Nov 18 in Digital Logic Shashank Rustagi 25.1k views
12 votes
4 answers
6
In $16$-bit $2$’s complement representation, the decimal number $-28$ is: $1111 \: 1111 \: 0001 \: 1100$ $0000 \: 0000 \: 1110 \: 0100$ $1111 \: 1111 \: 1110 \: 0100$ $1000 \: 0000 \: 1110 \: 0100$
answered Nov 17 in Digital Logic Ronak.e3 4.4k views
4 votes
5 answers
7
Consider the Boolean function $z(a,b,c)$. Which one of the following minterm lists represents the circuit given above? $z=\sum (0,1,3,7)$ $z=\sum (1,4,5,6,7)$ $z=\sum (2,4,5,6,7)$ $z=\sum (2,3,5)$
answered Nov 17 in Digital Logic Ronak.e3 1.9k views
0 votes
3 answers
8
A RAM chip has a capacity of $1024$ words of $8$ bits each $(1K \times 8)$. The number of $2 \times 4$ decoders with enable line needed to construct a $32 K \times 8$ RAM from $1K \times 8$ RAM is $4$ $5$ $6$ $7$
answered Nov 15 in Digital Logic the_psycho_scientist 609 views
20 votes
7 answers
9
What is the final value stored in the linear feedback shift register if the input is $101101$? $0110$ $1011$ $1101$ $1111$
answered Nov 14 in Digital Logic Shashank Rustagi 2.8k views
0 votes
2 answers
10
23 votes
6 answers
11
Consider the circuit given below with initial state $Q_0=1, Q_1=Q_2=0$. The state of the circuit is given by the value $4Q_2+2Q_1+Q_0$ Which one of the following is correct state sequence of the circuit? $1, 3, 4, 6, 7, 5, 2$ $1, 2, 5, 3, 7, 6, 4$ $1, 2, 7, 3, 5, 6, 4$ $1, 6, 5, 7, 2, 3, 4$
answered Oct 31 in Digital Logic Ronak.e3 4.7k views
38 votes
9 answers
12
In an $SR$ latch made by cross-coupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in $Q = 0, Q' = 1$ $Q = 1, Q' = 0$ $Q = 1, Q' = 1$ Indeterminate states
answered Oct 18 in Digital Logic vinitkumar 10.6k views
0 votes
1 answer
13
How can I construct a function table and excitation table from the given realisation, Please explain
answered Oct 13 in Digital Logic Vaibhav04 202 views
12 votes
3 answers
14
If the state machine described in figure should have a stable state, the restriction on the inputs is given by $a.b=1$ $a+b=1$ $\bar{a} + \bar{b} =0$ $\overline{a.b}=1$ $\overline{a+b} =1$
answered Oct 4 in Digital Logic Pratyush Priyam Kuan 3k views
24 votes
4 answers
15
What is the boolean expression for the output $f$ of the combinational logic circuit of NOR gates given below? $\overline{Q+R}$ $\overline{P+Q}$ $\overline{P+R}$ $\overline{P+Q+R}$
answered Oct 3 in Digital Logic Mohitdas 5.5k views
65 votes
6 answers
16
Consider numbers represented in 4-bit Gray code. Let $ h_{3}h_{2}h_{1}h_{0}$ be the Gray code representation of a number $n$ and let $ g_{3}g_{2}g_{1}g_{0}$ be the Gray code of $ (n+1)(modulo 16)$ ... $ g_{3}(h_{3}h_{2}h_{1}h_{0})=\sum (0,1,6,7,10,11,12,13) $
answered Sep 29 in Digital Logic Pratyush Priyam Kuan 9.5k views
32 votes
10 answers
17
Let, $x_{1} ⊕ x_{2} ⊕ x_{3} ⊕ x_{4}= 0$ where $x_{1}, x_{2}, x_{3}, x_{4}$ are Boolean variables, and $⊕$ is the XOR operator. Which one of the following must always be TRUE? $x_{1}x_{2}x_{3}x_{4} = 0$ $x_{1}x_{3} + x_{2} = 0$ $\bar{x}_{1} ⊕ \bar{x}_{3} = \bar{x}_{2} ⊕ \bar{x}_{4}$ $x_{1} + x_{2} + x_{3} + x_{4} = 0$
answered Sep 29 in Digital Logic shivam001 5.7k views
23 votes
3 answers
18
The maximum gate delay for any output to appear in an array multiplier for multiplying two $n$ bit numbers is $O(n^2)$ $O(n)$ $O(\log n)$ $O(1)$
answered Sep 29 in Digital Logic Pratyush Priyam Kuan 4.9k views
27 votes
3 answers
19
Consider the binary code that consists of only four valid codewords as given below: 00000, 01011, 10101, 11110 Let the minimum Hamming distance of the code $p$ and the maximum number of erroneous bits that can be corrected by the code be $q$. Then the values of $p$ and $q$ are $p=3$ and $q=1$ $p=3$ and $q=2$ $p=4$ and $q=1$ $p=4$ and $q=2$
answered Sep 29 in Digital Logic shivam001 6.9k views
33 votes
5 answers
20
The number of full and half-adders required to add $16$-bit numbers is $8$ half-adders, $8$ full-adders $1$ half-adder, $15$ full-adders $16$ half-adders, $0$ full-adders $4$ half-adders, $12$ full-adders
answered Sep 24 in Digital Logic Mitali gupta 9.1k views
2 votes
3 answers
21
A $3$ line to $8$ line Decoder is used to implement a $3$-variable Boolean function as shown in figure. The simplified form of output $Y$ is. $\bar{X}Y + \bar{Y}Z + XY\bar{Z}$ $\bar{X}Z +\bar{Y}Z + XYZ$ $X\bar{Y} + X\bar{Z} +\bar{X}YZ$ $X\bar{Y} + X\bar{Z} + \bar{X}Y\bar{Z}$
answered Sep 23 in Digital Logic prakashm 612 views
1 vote
3 answers
22
Consider a full-adder with the following input values : $x=1, y=0$ and $C_i$(carry input)$=0$ $x=0, y=1$ and $C_i =1$ Compute the value of S(sum) and $C_o$ (carry output) for the above input values : $S=1, C_o=0$ and $S=0, C_o=1$ $S=0, C_o=0$ and $S=1, C_o=1$ $S=1, C_o=1$ and $S=0, C_o=0$ $S=0, C_o=1$ and $S=1, C_o=0$
answered Sep 22 in Digital Logic shivam001 1.4k views
0 votes
1 answer
24
A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is $\text{S-R}$ Flip-flop with inputs $X = R$ and $Y=S$ $\text{S-R}$ Flip-flop with inputs $X = S$ and $Y=R$ $\text{J-K}$ Flip-flop with inputs $X = J$ and $Y=K$ $\text{J-K}$ Flip-flop with inputs $X = K$ and $Y=J$
answered Sep 19 in Digital Logic Sharma9999999 205 views
0 votes
1 answer
25
Simplify the Following boolean function by means of the tabulation method. (a) P(A,B,C,D,E,F,G)=$\sum(20,28,52,60)$ (b) P(A,B,C,D,E,F,G)= $\sum(20,28,38,39,52,60,102,103,127)$ (C) P(A,B,C,D,E,F) = $\sum(6,9,13,18,19,25,27,29,41,45,57,61)$
answered Sep 16 in Digital Logic Vishnu007 546 views
0 votes
2 answers
27
Addition of all gray code to convert decimal(0-9) into gray code is a)129 b) 108 c) 69 d) 53
answered Sep 12 in Digital Logic shivamjaiswal64 1.1k views
1 vote
5 answers
28
3 votes
10 answers
32
0 votes
2 answers
35
0 votes
1 answer
36
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
answered Sep 8 in Digital Logic mohit rathore 205 views
19 votes
5 answers
37
A circuit outputs a digit in the form of $4$ bits. $0$ is represented by $0000$, $1$ by $0001$, …, $9$ by $1001$. A combinational circuit is to be designed which takes these $4$ bits as input and outputs $1$ if the digit $\geq$ $5$, and $0$ otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required? $2$ $3$ $4$ $5$
answered Sep 6 in Digital Logic Nikhil_dhama 4.4k views
0 votes
1 answer
39
A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is $\text{S-R}$ Flip-flop with inputs $X = R$ and $Y=S$ $\text{S-R}$ Flip-flop with inputs $X = S$ and $Y=R$ $\text{J-K}$ Flip-flop with inputs $X = J$ and $Y=K$ $\text{J-K}$ Flip-flop with inputs $X = K$ and $Y=J$
answered Sep 5 in Digital Logic mohit rathore 446 views
2 votes
1 answer
40
Delay of AND gate = 1ns, FF = 2ns. What is the maximum clock rate possible to apply so that counter will work satisfactorily? a) 143 MHz b) 200 MHz c) 333 MHz
answered Sep 5 in Digital Logic suvradip das 338 views
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