search
Log In

Recent questions and answers in Digital Logic

2 votes
3 answers
1
A $3$ line to $8$ line Decoder is used to implement a $3$-variable Boolean function as shown in figure. The simplified form of output $Y$ is. $\bar{X}Y + \bar{Y}Z + XY\bar{Z}$ $\bar{X}Z +\bar{Y}Z + XYZ$ $X\bar{Y} + X\bar{Z} +\bar{X}YZ$ $X\bar{Y} + X\bar{Z} + \bar{X}Y\bar{Z}$
answered 5 hours ago in Digital Logic prakashm 494 views
1 vote
3 answers
2
Consider a full-adder with the following input values : $x=1, y=0$ and $C_i$(carry input)$=0$ $x=0, y=1$ and $C_i =1$ Compute the value of S(sum) and $C_o$ (carry output) for the above input values : $S=1, C_o=0$ and $S=0, C_o=1$ $S=0, C_o=0$ and $S=1, C_o=1$ $S=1, C_o=1$ and $S=0, C_o=0$ $S=0, C_o=1$ and $S=1, C_o=0$
answered 1 day ago in Digital Logic shivam001 1.3k views
0 votes
1 answer
4
A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is $\text{S-R}$ Flip-flop with inputs $X = R$ and $Y=S$ $\text{S-R}$ Flip-flop with inputs $X = S$ and $Y=R$ $\text{J-K}$ Flip-flop with inputs $X = J$ and $Y=K$ $\text{J-K}$ Flip-flop with inputs $X = K$ and $Y=J$
answered 3 days ago in Digital Logic Sharma9999999 42 views
0 votes
1 answer
5
Simplify the Following boolean function by means of the tabulation method. (a) P(A,B,C,D,E,F,G)=$\sum(20,28,52,60)$ (b) P(A,B,C,D,E,F,G)= $\sum(20,28,38,39,52,60,102,103,127)$ (C) P(A,B,C,D,E,F) = $\sum(6,9,13,18,19,25,27,29,41,45,57,61)$
answered 6 days ago in Digital Logic Vishnu007 335 views
0 votes
2 answers
7
Addition of all gray code to convert decimal(0-9) into gray code is a)129 b) 108 c) 69 d) 53
answered Sep 12 in Digital Logic shivamjaiswal64 1k views
1 vote
5 answers
8
1 vote
3 answers
9
0 votes
2 answers
10
1 vote
3 answers
11
3 votes
10 answers
12
0 votes
2 answers
15
0 votes
1 answer
16
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
answered Sep 8 in Digital Logic mohit rathore 48 views
17 votes
5 answers
17
A circuit outputs a digit in the form of $4$ bits. $0$ is represented by $0000$, $1$ by $0001$, …, $9$ by $1001$. A combinational circuit is to be designed which takes these $4$ bits as input and outputs $1$ if the digit $\geq$ $5$, and $0$ otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required? $2$ $3$ $4$ $5$
answered Sep 6 in Digital Logic Nikhil_dhama 3.6k views
3 votes
4 answers
18
Consider the Boolean function $z(a,b,c)$. Which one of the following minterm lists represents the circuit given above? $z=\sum (0,1,3,7)$ $z=\sum (1,4,5,6,7)$ $z=\sum (2,4,5,6,7)$ $z=\sum (2,3,5)$
answered Sep 6 in Digital Logic Madhav 1.4k views
0 votes
1 answer
20
A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is $\text{S-R}$ Flip-flop with inputs $X = R$ and $Y=S$ $\text{S-R}$ Flip-flop with inputs $X = S$ and $Y=R$ $\text{J-K}$ Flip-flop with inputs $X = J$ and $Y=K$ $\text{J-K}$ Flip-flop with inputs $X = K$ and $Y=J$
answered Sep 5 in Digital Logic mohit rathore 90 views
2 votes
1 answer
21
Delay of AND gate = 1ns, FF = 2ns. What is the maximum clock rate possible to apply so that counter will work satisfactorily? a) 143 MHz b) 200 MHz c) 333 MHz
answered Sep 5 in Digital Logic suvradip das 279 views
0 votes
2 answers
22
0 votes
2 answers
25
0 votes
2 answers
26
is given ans correct ?
answered Sep 4 in Digital Logic S.R. 122 views
39 votes
10 answers
28
In the sequential circuit shown below, if the initial value of the output $Q_1Q_0$ is $00$. What are the next four values of $Q_1Q_0$? $11$, $10$, $01$, $00$ $10$, $11$, $01$, $00$ $10$, $00$, $01$, $11$ $11$, $10$, $00$, $01$
answered Sep 2 in Digital Logic Musa 10k views
0 votes
3 answers
29
Assume that the EXCLUSIVE-OR gate has a propagation delay of 20ns and that the AND and OR gates have a Propagation delay of 10ns. What is the total Propagation delay time in the four-bit adder of the figure given below?
answered Aug 31 in Digital Logic Musa 229 views
0 votes
3 answers
31
A 1-bit full adder circuit takes 5 ns to generate the carry-out bit and 10 ns for the sum-bit. When 4, 1-bit full adders are cascaded, the maximum rate of additions per second will be _______ × 107.
answered Aug 31 in Digital Logic Musa 187 views
0 votes
0 answers
32
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
asked Aug 28 in Digital Logic Lakshman Patel RJIT 22 views
1 vote
1 answer
33
0 votes
1 answer
36
1 vote
2 answers
38
1 vote
1 answer
39
In a ripple counter using edge triggered $JK$ flip-flops, the pulse input is applied to the clock input of all flip-flops clock input of one flip-flop $J$ and $K$ inputs of all flip-flops $J$ and $K$ inputs of one flip flop
asked Mar 31 in Digital Logic Lakshman Patel RJIT 200 views
1 vote
1 answer
40
A decimal number has $30$ digits. Approximately, how many digits would the binary representation have? $30$ $60$ $90$ $120$
asked Mar 31 in Digital Logic Lakshman Patel RJIT 222 views
To see more, click for all the questions in this category.
...