# Recent questions and answers in Digital Logic 1 vote
1 answer
1
A synchronous sequential circuit is to be designed to detect a bit sequence 0101 (overlapping sequence is included ). Every time this sequence is detected, the circuit produces an output ‘1’. What is the Minimum number of states that the circuit must have ? (a) 4 (b) 5 (c) 6 (d) 7
35 votes
6 answers
2
The number of full and half-adders required to add $16$-bit numbers is $8$ half-adders, $8$ full-adders $1$ half-adder, $15$ full-adders $16$ half-adders, $0$ full-adders $4$ half-adders, $12$ full-adders
1 vote
2 answers
3
a 4 bit serial in parallel out shift register is used with a feedback as shown in figure below the shifting sequences q3 - >q2-> q1- > q0. if the output is initially 0000, the no of clock pulses after which t the output will repeat itself is
3 votes
2 answers
4
Consider a Boolean function $f(w,x,y,z)$ such that $\begin{array}{lll} f(w,0,0,z) & = & 1 \\ f(1,x,1,z) & =& x+z \\ f(w,1,y,z) & = & wz +y \end{array}$The number of literals in the minimal sum-of-products expression of $f$ is _________
1 vote
2 answers
5
How to calculate the total number of flip flops in a synchronous Counter having switching sequence 0-6-2-5-3 (back to 0) ?
1 vote
1 answer
6
An example of a self complementing code is : $8421$ code Gray code Excess-$3$ code $7421$ code
0 votes
2 answers
7
A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of 2 × 4 decoders with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is Note:it is previous yr gate ques , i asked it again bcz that answer i did not get. After getting answer i hide it. So don't close it.
0 votes
1 answer
8
The combinational circuit given below is implemented with two NAND gates. To which of the following individual gates is its equivalent? NOT OR AND XOR
0 votes
1 answer
9
The hexadecimal equivalent of $(10111)_2\times(1110)_2$ is : $150$ $241$ $142$ $101011110$
1 vote
3 answers
10
The octal equivalent of hexadecimal $\text{(A.B)}_{16}$ is : $47.21$ $12.74$ $12.71$ $17.21$
1 vote
2 answers
11
The Boolean expression $\bar{x}\bar{y}z+yz+xz$ is equivalent to : x y z $x+y+z$
2 votes
3 answers
12
The logic expression for the output of the circuit shown in the figure is $\bar{A} \bar{C}+ \bar{B}\bar{C}+CD$ $A\bar{C}+B\bar{C}+\bar{C}D$ $ABC + \bar{C}\bar{D}$ $\bar{A}\bar{B}+\bar{B}\bar{C}+\bar{C}\bar{D}$
0 votes
2 answers
13
The function represented by the $\text{k}$-map given below is $A ⋅ B$ $AB + BC + CA$ $\overline{B \bigoplus C}$ $A ⋅ B ⋅ C$
0 votes
5 answers
14
The hexadecimal equivalent of the octal number $2357$ is : $2EE$ $2FF$ $4EF$ $4FE$
2 votes
2 answers
15
Consider the following Boolean expression. $F=(X+Y+Z)(\overline X +Y)(\overline Y +Z)$ Which of the following Boolean expressions is/are equivalent to $\overline F$ (complement of $F$)? $(\overline X +\overline Y +\overline Z)(X+\overline Y)(Y+\overline Z)$ $X\overline Y + \overline Z$ $(X+\overline Z)(\overline Y +\overline Z)$ $X\overline Y +Y\overline Z + \overline X \overline Y \overline Z$
0 votes
1 answer
16
Is'nt all options are correct??
19 votes
7 answers
17
Consider the two cascade $2$ to $1$ multiplexers as shown in the figure . The minimal sum of products form of the output $X$ is $\overline{P} \ \overline {Q}+PQR$ $\overline{P} \ {Q}+QR$ $PQ +\overline{P} \ \overline{Q}R$ $\overline{Q} \ \overline{R} + PQR$
22 votes
4 answers
18
The following circuit implements a two-input AND gate using two $2-1$ multiplexers. What are the values of $X_1, X_2, X_3$? $X_1 = b, X_2 = 0, X_3 = a$ $X_1 = b, X_2 = 1, X_3 = b$ $X_1 = a, X_2 = b, X_3 = 1$ $X_1 = a, X_2 = 0, X_3 = b$
51 votes
8 answers
19
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of $n$ variables. What is the minimum size of the multiplexer needed? $2^n$ line to $1$ line $2^{n+1}$ line to $1$line $2^{n-1}$ line to $1$line $2^{n-2}$ line to $1$line
1 vote
1 answer
20
Add and Multiply the following number without converting them into decimal $(367) _8 and (815) _8$ $(15F) _{16} and (A7) _{16}$ ($110110) _2 And (110101) _2$
0 votes
1 answer
21
consider two 4-bit numbers A=A3 A2 A1 A0 and B=B3 B2 B1 B0 and the expression x=AiBi+AiBi for i=0,1,2,3. the expression A3B3+x3A2B2+x3x2A1B1+x3x2x1A0B0 evaluates to 1 if a- A=b b-A!=b c-A>B d-A<B
0 votes
1 answer
22
Find the 9’s complement of the 8 digit decimal numbers. 12349876 00980100 90009951 00000000
18 votes
3 answers
23
Design a logic circuit to convert a single digit BCD number to the number modulo six as follows (Do not detect illegal input): Write the truth table for all bits. Label the input bits $I_1, I_2, \ldots$ with $I_1$ as the least significant bit. Label the output bits ... truth. Draw one circuit for each output bit using, altogether, two two-input AND gates, one two-input OR gate and two NOT gates.
3 votes
4 answers
24
f(A,B,C,D)=∏M(0,1,3,4,5,7,9,11,12,13,14,15) is a max-term representation of a Boolean function f(A,B,C,D) where A is the MSB and D is the LSB. The equivalent minimized representation of this function is (A+C¯+D)(A¯+B+D)(A+C¯+D)(A¯+B+D) AC¯D+A¯BD+A¯BC A¯CD¯+AB¯CD¯+AB¯C¯D¯ (B+C¯+D)(A+B¯+C¯+D)(A¯+B+C+D)
0 votes
4 answers
25
Is Y' + Z' same as (YZ)' ? Please explain this concept of compliments..!!
1 vote
2 answers
26
Which of the following flip flops is used as a 1-bit memory element? (A) T flip flop (B) SR flip flop (C) D flip flop (D) JK flip flop
6 votes
3 answers
27
If there are $m$ input lines and $n$ output lines for a decoder that is used to uniquely address a byte addressable $1$ KB RAM, then the minimum value of $m+n$ is ________ .
5 votes
3 answers
28
The following circuit compares two $2$-bit binary numbers, $X$ and $Y$ represented by $X_1X_0$ and $Y_1Y_0$ respectively. ($X_0$ and $Y_0$ represent Least Significant Bits) Under what conditions $Z$ will be $1$? $X>Y$ $X<Y$ $X=Y$ $X!=Y$
0 votes
2 answers
29
To make the following circuit a tautology ‘?’ marked box should be OR gate AND gate NAND gate EX-OR gate
0 votes
3 answers
30
Which one of the following is the function of a multiplexer? To decode information To select $1$ out of $N$ input data sources and to transmit it to single channel To transmit data on $N$ lines To perform serial to parallel conversion
1 vote
2 answers
31
What will be the equation of the given K-map? $A’B’D’+C’D+AB’C’$ $B’CD’+AB’C’+A’C’$ $B’D’+C’D$ $C’D+B’CD’$
2 votes
3 answers
32
The Circuit is equivalent to: $OR$ Gate $NOR$ Gate $AND$ Gate $EX-OR$ Gate
1 vote
3 answers
33
The Decimal equivalent of the Hexadecimal number $(AC7B)​_{16​}$ is: $32564$ $44155$ $50215$ $43562$
1 vote
2 answers
34
What will be the final output of D flip-Flop if the input string is $0010011100$? $1$ $0$ Don’t Care None of the above
1 vote
3 answers
35
How many inputs are required in Full Adder Circuit? $2$ $3$ More than two inputs None of the above
2 votes
3 answers
36
The format of the single-precision floating point representation of a real number as per the $\text{IEEE 754}$ ... $=00000000$ and mantissa $=0000000000000000000000001$ exponent $=00000001$ and mantissa $=0000000000000000000000000$ exponent $=00000001$ and mantissa $=0000000000000000000000001$
3 votes
4 answers
37
Which one of the following circuits implements the Boolean function given below? $f(x,y,z) = m_0+m_1+m_3+m_4+m_5+m_6$, where $m_i$ is the $i^{\text{th}}$ minterm.
0 votes
1 answer
38
Assign a binary number to some orderly manner to the 52 playing cards. use the minimum number of the bits.
12 votes
2 answers
39
Is there any systematic approach to find the minimum number of two input NAND gates and two input NOR gates to be used to impelement a binary expression? If there then please elaborate it for the function Y = A'B+B'C+CD' .
1 vote
3 answers
40
Consider a $3$-bit counter, designed using $T$ flip-flops, as shown below: Assuming the initial state of the counter given by $\text{PQR}$ as $000$, what are the next three states? $011,101,000$ $001,010,111$ $011,101,111$ $001,010,000$
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