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Recent questions and answers in Digital Logic

1 vote
1 answer
1
A synchronous sequential circuit is to be designed to detect a bit sequence 0101 (overlapping sequence is included ). Every time this sequence is detected, the circuit produces an output ‘1’. What is the Minimum number of states that the circuit must have ? (a) 4 (b) 5 (c) 6 (d) 7
answered 5 days ago in Digital Logic AKS2209 1.4k views
35 votes
6 answers
2
The number of full and half-adders required to add $16$-bit numbers is $8$ half-adders, $8$ full-adders $1$ half-adder, $15$ full-adders $16$ half-adders, $0$ full-adders $4$ half-adders, $12$ full-adders
answered Jun 9 in Digital Logic ShouvikSVK 13.3k views
1 vote
2 answers
3
a 4 bit serial in parallel out shift register is used with a feedback as shown in figure below the shifting sequences q3 - >q2-> q1- > q0. if the output is initially 0000, the no of clock pulses after which t the output will repeat itself is
answered Jun 6 in Digital Logic Abhrajyoti00 597 views
3 votes
2 answers
4
Consider a Boolean function $f(w,x,y,z)$ such that $\begin{array}{lll} f(w,0,0,z) & = & 1 \\ f(1,x,1,z) & =& x+z \\ f(w,1,y,z) & = & wz +y \end{array}$The number of literals in the minimal sum-of-products expression of $f$ is _________
answered May 31 in Digital Logic Deepakk Poonia (Dee) 1.2k views
1 vote
2 answers
5
How to calculate the total number of flip flops in a synchronous Counter having switching sequence 0-6-2-5-3 (back to 0) ?
answered May 25 in Digital Logic Sonu12345 461 views
1 vote
1 answer
6
An example of a self complementing code is : $8421$ code Gray code Excess-$3$ code $7421$ code
answered May 23 in Digital Logic Sachin85 302 views
0 votes
2 answers
7
A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of 2 × 4 decoders with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is Note:it is previous yr gate ques , i asked it again bcz that answer i did not get. After getting answer i hide it. So don't close it.
answered May 17 in Digital Logic Abhishek2000 1.6k views
0 votes
1 answer
8
0 votes
1 answer
9
The hexadecimal equivalent of $(10111)_2\times(1110)_2$ is : $150$ $241$ $142$ $101011110$
answered May 14 in Digital Logic Hira Thakur 224 views
1 vote
3 answers
10
1 vote
2 answers
11
2 votes
3 answers
12
The logic expression for the output of the circuit shown in the figure is $\bar{A} \bar{C}+ \bar{B}\bar{C}+CD$ $A\bar{C}+B\bar{C}+\bar{C}D$ $ABC + \bar{C}\bar{D}$ $\bar{A}\bar{B}+\bar{B}\bar{C}+\bar{C}\bar{D}$
answered May 12 in Digital Logic Hira Thakur 964 views
0 votes
2 answers
13
The function represented by the $\text{k}$-map given below is $A ⋅ B$ $AB + BC + CA$ $\overline{B \bigoplus C}$ $A ⋅ B ⋅ C$
answered May 12 in Digital Logic Hira Thakur 849 views
0 votes
5 answers
14
2 votes
2 answers
15
Consider the following Boolean expression. $F=(X+Y+Z)(\overline X +Y)(\overline Y +Z)$ Which of the following Boolean expressions is/are equivalent to $\overline F$ (complement of $F$)? $(\overline X +\overline Y +\overline Z)(X+\overline Y)(Y+\overline Z)$ $X\overline Y + \overline Z$ $(X+\overline Z)(\overline Y +\overline Z)$ $X\overline Y +Y\overline Z + \overline X \overline Y \overline Z$
answered May 11 in Digital Logic Hira Thakur 701 views
0 votes
1 answer
16
19 votes
7 answers
17
Consider the two cascade $2$ to $1$ multiplexers as shown in the figure . The minimal sum of products form of the output $X$ is $\overline{P} \ \overline {Q}+PQR$ $\overline{P} \ {Q}+QR$ $PQ +\overline{P} \ \overline{Q}R$ $\overline{Q} \ \overline{R} + PQR$
answered May 3 in Digital Logic varunrajarathnam 5.6k views
22 votes
4 answers
18
The following circuit implements a two-input AND gate using two $2-1$ multiplexers. What are the values of $X_1, X_2, X_3$? $X_1 = b, X_2 = 0, X_3 = a$ $X_1 = b, X_2 = 1, X_3 = b$ $X_1 = a, X_2 = b, X_3 = 1$ $X_1 = a, X_2 = 0, X_3 = b$
answered May 3 in Digital Logic varunrajarathnam 3.8k views
51 votes
8 answers
19
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of $n$ variables. What is the minimum size of the multiplexer needed? $2^n$ line to $1$ line $2^{n+1}$ line to $1$line $2^{n-1}$ line to $1$line $2^{n-2}$ line to $1$line
answered May 2 in Digital Logic varunrajarathnam 17.5k views
1 vote
1 answer
20
0 votes
1 answer
21
consider two 4-bit numbers A=A3 A2 A1 A0 and B=B3 B2 B1 B0 and the expression x=AiBi+AiBi for i=0,1,2,3. the expression A3B3+x3A2B2+x3x2A1B1+x3x2x1A0B0 evaluates to 1 if a- A=b b-A!=b c-A>B d-A<B
answered Apr 29 in Digital Logic Rohan Agrawal 435 views
18 votes
3 answers
23
Design a logic circuit to convert a single digit BCD number to the number modulo six as follows (Do not detect illegal input): Write the truth table for all bits. Label the input bits $I_1, I_2, \ldots$ with $I_1$ as the least significant bit. Label the output bits ... truth. Draw one circuit for each output bit using, altogether, two two-input AND gates, one two-input OR gate and two NOT gates.
answered Apr 10 in Digital Logic jatinmittal199510 1.7k views
3 votes
4 answers
24
f(A,B,C,D)=∏M(0,1,3,4,5,7,9,11,12,13,14,15) is a max-term representation of a Boolean function f(A,B,C,D) where A is the MSB and D is the LSB. The equivalent minimized representation of this function is (A+C¯+D)(A¯+B+D)(A+C¯+D)(A¯+B+D) AC¯D+A¯BD+A¯BC A¯CD¯+AB¯CD¯+AB¯C¯D¯ (B+C¯+D)(A+B¯+C¯+D)(A¯+B+C+D)
answered Apr 9 in Digital Logic Yogitha V 4.6k views
0 votes
4 answers
25
Is Y' + Z' same as (YZ)' ? Please explain this concept of compliments..!!
answered Apr 4 in Digital Logic heisenberggg 244 views
1 vote
2 answers
26
Which of the following flip flops is used as a 1-bit memory element? (A) T flip flop (B) SR flip flop (C) D flip flop (D) JK flip flop
answered Apr 4 in Digital Logic heisenberggg 388 views
6 votes
3 answers
27
If there are $m$ input lines and $n$ output lines for a decoder that is used to uniquely address a byte addressable $1$ KB RAM, then the minimum value of $m+n$ is ________ .
answered Apr 4 in Digital Logic heisenberggg 4.1k views
5 votes
3 answers
28
The following circuit compares two $2$-bit binary numbers, $X$ and $Y$ represented by $X_1X_0$ and $Y_1Y_0$ respectively. ($X_0$ and $Y_0$ represent Least Significant Bits) Under what conditions $Z$ will be $1$? $X>Y$ $X<Y$ $X=Y$ $X!=Y$
answered Apr 4 in Digital Logic heisenberggg 1k views
0 votes
3 answers
30
Which one of the following is the function of a multiplexer? To decode information To select $1$ out of $N$ input data sources and to transmit it to single channel To transmit data on $N$ lines To perform serial to parallel conversion
answered Apr 4 in Digital Logic heisenberggg 474 views
1 vote
2 answers
31
2 votes
3 answers
36
The format of the single-precision floating point representation of a real number as per the $\text{IEEE 754}$ ... $=00000000$ and mantissa $=0000000000000000000000001$ exponent $=00000001$ and mantissa $=0000000000000000000000000$ exponent $=00000001$ and mantissa $=0000000000000000000000001$
answered Apr 4 in Digital Logic gatecse 1k views
3 votes
4 answers
37
12 votes
2 answers
39
Is there any systematic approach to find the minimum number of two input NAND gates and two input NOR gates to be used to impelement a binary expression? If there then please elaborate it for the function Y = A'B+B'C+CD' .
answered Mar 16 in Digital Logic Bhartendu Kumar 19.9k views
1 vote
3 answers
40
Consider a $3$-bit counter, designed using $T$ flip-flops, as shown below: Assuming the initial state of the counter given by $\text{PQR}$ as $000$, what are the next three states? $011,101,000$ $001,010,111$ $011,101,111$ $001,010,000$
answered Feb 27 in Digital Logic Harshq 667 views
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