Recent questions and answers in Digital Logic / GATE Overflow for GATE CSE

0 votes

1 answer

1

Expression Evaluation
44. Evaluate each of these expressions. a) 1 1000 ∧ (0 1011 ∨ 1 1011) b) (0 1111 ∧ 1 0101) ∨ 0 1000 c) (0 1010 ⊕ 1 1011) ⊕ 0 1000 d) (1 1011 ∨ 0 1010) ∧ (1 0001 ∨ 1 1011)

44. Evaluate each of these expressions. a) 1 1000 ∧ (0 1011 ∨ 1 1011) b) (0 1111 ∧ 1 0101) ∨ 0 1000 c) (0 1010 ⊕ 1 1011) ⊕ 0 1000 d) (1 1011 ∨ 0 1010) ∧ (...

Bhaskar_Saini

53 views

Bhaskar_Saini answered 2 days ago

26 votes

5 answers

2

GATE CSE 1987 | Question: 1-II
The total number of Boolean functions which can be realised with four variables is: $4$ $17$ $256$ $65, 536$

The total number of Boolean functions which can be realised with four variables is:$4$$17$$256$$65, 536$

Vivek jangir

5.2k views

Vivek jangir answered 6 days ago

0 votes

0 answers

3

question
Design a circuit with 4 inputs that has outputs with a binary value equal to the number of inputs that are HIGH.

Design a circuit with 4 inputs that has outputs with a binary value equal to the number of inputs that are HIGH.

aaryannn

41 views

aaryannn asked May 5

6 votes

6 answers

4

ISRO2014-15
Consider the logic circuit given below: $\text{Q =}$ __________? $\overline{\text{A}} \text{C} + \text{B} \overline{\text{C}} +\text{CD}$ $\text{ABC} + \overline{\text{C}} \text{D}$ $\text{AB + B} \overline{\text{C}} + \text{B} \overline{\text{D}}$ $\text{A} \overline{\text{B}} + \text{A} \overline{\text{C}} + \overline{\text{C}} \text{D}$

Consider the logic circuit given below:$\text{Q =}$ __________?$\overline{\text{A}} \text{C} + \text{B} \overline{\text{C}} +\text{CD}$$\text{ABC} + \overline{\text{C}} \...

mnuAbhi

4.0k views

mnuAbhi answered May 4

24 votes

5 answers

5

GATE CSE 1992 | Question: 01-i
The Boolean function in sum of products form where K-map is given below (figure) is _______

The Boolean function in sum of products form where K-map is given below (figure) is _______

Vivek jangir

5.4k views

Vivek jangir answered May 4

9 votes

2 answers

6

ISRO2016-7
The minimum number of $\text{NAND}$ gates required to implement the Boolean function $A + A\overline{B} + A\overline{B}C$ is equal to $0$ (Zero) $1$ $4$ $7$

The minimum number of $\text{NAND}$ gates required to implement the Boolean function $A + A\overline{B} + A\overline{B}C$ is equal to$0$ (Zero)$1$$4$$7$

mnuAbhi

7.2k views

mnuAbhi answered May 3

2 votes

4 answers

7

GATE CSE 2024 | Set 2 | Question: 20
For a Boolean variable $x$, which of the following statements is/are FALSE? $x .1=x$ $x+1=x$ $x \cdot x=0$ $x+\bar{x}=1$

For a Boolean variable $x$, which of the following statements is/are FALSE?$x .1=x$$x+1=x$$x \cdot x=0$$x+\bar{x}=1$

MukulGupta

2.4k views

MukulGupta answered Apr 29

1 votes

0 answers

8

Digital Logic
What is the maximum n-bit number in base x ,when represented in decimal(10)?

What is the maximum n-bit number in base x ,when represented in decimal(10)?

deba1014

118 views

deba1014 asked Apr 12

0 votes

0 answers

9

Convert the following decimal numbers to 8-bit two’s complement numbers or indicate that the number would overflow the range.

lolok

118 views

lolok asked Apr 4

0 votes

2 answers

10

how is the minimum number of NOR gates required is 5?

ravi2002

242 views

ravi2002 answered Mar 29

3 votes

2 answers

11

GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 27
What statement is correct for $f(A, B)$ in the following circuit? $f(A, B)=\overline{\overline{A \cdot B} \cdot(A+B)}$ when Control $=1$ $f(A, B)=A \cdot B$ when Control $=0$ $f(A, B)=\overline{A}+\overline{B}$ when Control $=1$ $f(A, B)=\overline{A} \cdot \overline{B}$ when Control $=0$

What statement is correct for $f(A, B)$ in the following circuit?$f(A, B)=\overline{\overline{A \cdot B} \cdot(A+B)}$ when Control $=1$$f(A, B)=A \cdot B$ when Control $=...

ravi2002

416 views

ravi2002 answered Mar 29

0 votes

0 answers

12

Exam
Design a 3-bit code to represent each of the six digits of the base-6 number system. Make the binary code self-complementing so that the 5's complement is obtained by changing 1's to 0's and Os to 1's in all bits of the coded numbers.

Design a 3-bit code to represent each of the six digits of the base-6 number system. Make the binary code self-complementing so that the 5's complement is obtained by cha...

Bubby

104 views

Bubby asked Mar 27

0 votes

1 answer

13

2421 code
in 2421 code for 5 is 1011 why not 0101 ?????????

in 2421 code for 5 is 1011 why not 0101 ?????????

Turban_trap

2.1k views

Turban_trap answered Mar 15

35 votes

5 answers

14

GATE IT 2005 | Question: 48
The circuit shown below implements a $\text{2-input}$ NOR gate using two $2-4$ MUX (control signal $1$ selects the upper input). What are the values of signals $x, y$ and $z$? $1, 0, B$ $1, 0, A$ $0, 1, B$ $0, 1, A$

The circuit shown below implements a $\text{2-input}$ NOR gate using two $2-4$ MUX (control signal $1$ selects the upper input). What are the values of signals $x, y$ and...

ANIL Kr.

7.8k views

ANIL Kr. answered Feb 23

2 votes

3 answers

15

GATE CSE 2024 | Set 1 | Question: 54
Consider a digital logic circuit consisting of three $2$-to-$1$ multiplexers $\text{M1, M2}$, and $\text{M3}$ as shown below. $\mathrm{X} 1$ and $\mathrm{X} 2$ are inputs of $\mathrm{M} 1$. $\text{X3}$ and $\text{X4}$ are inputs ... the number of combinations of $\mathrm{A}, \mathrm{B}, \mathrm{C}$ that give the output $\mathbf{Y}=\mathbf{1}$ is ____________.

Consider a digital logic circuit consisting of three $2$-to-$1$ multiplexers $\text{M1, M2}$, and $\text{M3}$ as shown below. $\mathrm{X} 1$ and $\mathrm{X} 2$ are inputs...

GauravRajpurohit

2.4k views

GauravRajpurohit answered Feb 18

3 votes

5 answers

16

GATE CSE 2024 | Set 1 | Question: 3
Consider a system that uses $5$ bits for representing signed integers in $2$ 's complement format. In this system, two integers $A$ and $B$ are represented as $A$=$01010$ and $B$=$11010$. Which one of the following operations will result in either an arithmetic overflow or an arithmetic underflow? $A+B$ $A-B$ $B-A$ $2 * B$

Consider a system that uses $5$ bits for representing signed integers in $2$ 's complement format. In this system, two integers $A$ and $B$ are represented as $A$=$01010$...

Psy Duck

4.2k views

Psy Duck answered Feb 17

2 votes

1 answer

17

GATE CSE 2024 | Set 1 | Question: 18
Consider the circuit shown below where the gates may have propagation delays. Assume that all signal transitions occur instantaneously and that wires have no delays. Which of the following statements about the circuit is/are CORRECT? With no propagation ... , the output $Y$ can have a transient logic Zero after $X$ transitions from logic One to logic Zero

Consider the circuit shown below where the gates may have propagation delays. Assume that all signal transitions occur instantaneously and that wires have no delays...

phaniphani

2.6k views

phaniphani answered Feb 16

1 votes

2 answers

18

GATE CSE 2024 | Set 1 | Question: 37
Consider a Boolean expression given by $\text{F(X, Y, Z)}=\sum(3,5,6,7)$. Which of the following statements is/are CORRECT? $\text{F(X, Y, Z)}=\Pi(0,1,2,4)$ $\text{F(X, Y, Z)=X Y+Y Z+X Z}$ $\text{F(X, Y, Z)}$ is independent of input $\text{Y}$ $\text{F(X, Y, Z)}$ is independent of input $\text{X}$

Consider a Boolean expression given by $\text{F(X, Y, Z)}=\sum(3,5,6,7)$.Which of the following statements is/are CORRECT?$\text{F(X, Y, Z)}=\Pi(0,1,2,4)$ $\text{F(X, Y, ...

Hira Thakur

2.2k views

Hira Thakur answered Feb 16

0 votes

1 answer

19

GATE CSE 2024 | Set 2 | Question: 4
The format of a single-precision floating-point number as per the $\text{IEEE 754}$ standard is: Sign Exponent Mantissa $(1 \mathrm{bit})$ $(8 \mathrm{bits})$ $(23 \mathrm{bits})$ Choose the largest floating- ... $0$ $11111111$ $11111111111111111111111$ Sign Exponent Mantissa $0$ $01111111$ $00000000000000000000000$

The format of a single-precision floating-point number as per the $\text{IEEE 754}$ standard is:Sign ExponentMantissa$(1 \mathrm{bit})$ $(8 \mathrm{bits})$ $(23 \ma...

supreetshukla

2.8k views

supreetshukla answered Feb 16

4 votes

1 answer

20

GATE CSE 2024 | Set 2 | Question: 40
Consider $4$-variable functions $f 1, f 2, f 3, f 4$ expressed in sum-of-minterms form as given below. $ \begin{array}{l} f 1=\sum(0,2,3,5,7,8,11,13) \\ f 2=\sum(1,3,5,7,11,13,15) \\ f 3=\sum(0,1,4,11) \\ f 4=\sum(0,2,6,13) \end{array} $ With ... $\boldsymbol{Y}=\sum(0,1,2,3,4,5,6,7)$ $\boldsymbol{Y}=\Pi(8,9,10,11,12,13,14,15)$

Consider $4$-variable functions $f 1, f 2, f 3, f 4$ expressed in sum-of-minterms form as given below.$$\begin{array}{l}f 1=\sum(0,2,3,5,7,8,11,13) \\f 2=\sum(1,3,5,7,11,...

Hira Thakur

2.1k views

Hira Thakur answered Feb 16

2 votes

1 answer

21

GATE CSE 2024 | Set 2 | Question: 39
Which of the following is/are EQUAL to $224$ in radix - $5$ (i.e., base - $5$) notation? $64$ in radix -10 $100$ in radix -8 $50$ in radix -16 $121$ in radix -7

Which of the following is/are EQUAL to $224$ in radix - $5$ (i.e., base - $5$) notation?$64$ in radix -10$100$ in radix -8$50$ in radix -16$121$ in radix -7

Hira Thakur

1.9k views

Hira Thakur answered Feb 16

4 votes

1 answer

22

GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 29
The largest positive number in 2's complement format represented with 8-bits is: $(\mathrm{FF})_{16}$ $(128)_{10}$ $(777)_8$ $(01111111)_2$

The largest positive number in 2's complement format represented with 8-bits is:$(\mathrm{FF})_{16}$$(128)_{10}$$(777)_8$$(01111111)_2$

TusharRana

531 views

TusharRana answered Feb 13

36 votes

5 answers

23

GATE CSE 2015 Set 3 | Question: 35
Consider the equation $(43)_x = (y3)_8$ where $x$ and $y$ are unknown. The number of possible solutions is _____

Consider the equation $(43)_x = (y3)_8$ where $x$ and $y$ are unknown. The number of possible solutions is _____

rajveer43

10.1k views

rajveer43 answered Feb 8

0 votes

1 answer

24

self doubts
how to simplify this boolean function i tend to get confuse on this given problem F(a,b,c)=(AB+AC)'+A'B'C

how to simplify this boolean function i tend to get confuse on this given problem F(a,b,c)=(AB+AC)'+A'B'C

Mrityudoot

235 views

Mrityudoot answered Feb 6

5 votes

1 answer

25

GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 30
Consider the function $f\left(x_1, x_2, x_3\right)=x_1 \cdot x_2 \cdot x_3+\bar{x}_1 \cdot \bar{x}_2 \cdot \bar{x}_3+\bar{x}_1 \cdot x_2 \cdot \bar{x}_3+\bar{x}_1 \cdot x_2 \cdot x_3$, what is the product of sum(POS) expression ...

Consider the function $f\left(x_1, x_2, x_3\right)=x_1 \cdot x_2 \cdot x_3+\bar{x}_1 \cdot \bar{x}_2 \cdot \bar{x}_3+\bar{x}_1 \cdot x_2 \cdot \bar{x}_3+\bar{x}_1 \cdot x...

squirrel69

517 views

squirrel69 answered Feb 6

2 votes

1 answer

26

GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 59
Consider the shift register circuit shown in below figure. Assume that $\mathbf{I}_3 \mathbf{I}_2 \mathbf{I}_1 \mathbf{I}_0=0101$ has been loaded in the 4-bit register using the parallel load mechanism (i.e., shift=0 ... consecutive positive edges of the clock signal we need to keep shift=1 such that zero detect is activated to a 1?

Consider the shift register circuit shown in below figure. Assume that $\mathbf{I}_3 \mathbf{I}_2 \mathbf{I}_1 \mathbf{I}_0=0101$ has been loaded in the 4-bit register us...

TotalBiscuit

567 views

TotalBiscuit answered Feb 6

5 votes

2 answers

27

GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 61
According to the IEEE standard, a 32-bit, single-precision, floating-point number $N$ is defined to be $ N=(-1)^S \times 1 . F \times 2^{E-127} $ where $S$ is the sign bit, $F$ the fractional mantissa, and $E$ the biased exponent. A floating- ... $\left(1-2^{-23}\right) * 2^{128}$ $\left(1+\left(1-2^{-23}\right)\right) * 2^{128}$

According to the IEEE standard, a 32-bit, single-precision, floating-point number $N$ is defined to be$$N=(-1)^S \times 1 . F \times 2^{E-127}$$where $S$ is the sign bit,...

Shreyas16

680 views

Shreyas16 answered Feb 6

2 votes

1 answer

28

GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 28
Consider function $\mathbf{G}(\mathbf{A}, \mathbf{B}, \mathbf{C})=\mathbf{A B}+\mathbf{B C}$. Let $\mathbf{F}(\mathbf{A}, \mathbf{B}, \mathbf{C})$ ... input to a 2-to-1 multiplexer. The correct implementation of $\mathbf{F}(\mathbf{A}, \mathbf{B}, \mathbf{C})$ is shown in:

Consider function $\mathbf{G}(\mathbf{A}, \mathbf{B}, \mathbf{C})=\mathbf{A B}+\mathbf{B C}$. Let $\mathbf{F}(\mathbf{A}, \mathbf{B}, \mathbf{C})$ be the dual of $\mathbf...

keshav_18

569 views

keshav_18 answered Feb 6

3 votes

0 answers

29

GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 60
The logic circuit above is used to compare two unsigned 2-bit numbers, $X_1 X_0=X$ and $Y_1 Y_0=Y$, where $X_0$ and $Y_0$ are the least significant bits. (A small circle on any line in a logic diagram indicates logical NOT.) Which of the following always makes the output $Z$ have the value 1? $X\gt Y$ $X\lt Y$ $X=Y$ $X \neq Y$

The logic circuit above is used to compare two unsigned 2-bit numbers, $X_1 X_0=X$ and $Y_1 Y_0=Y$, where $X_0$ and $Y_0$ are the least significant bits. (A small circle ...

GO Classes

353 views

GO Classes asked Feb 5

2 votes

3 answers

30

GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 59
For the circuit in the figure below, if the current state $\text{Q}_3\text{Q}_2\text{Q}_1\text{Q}_0$ is $6$ (in decimal) i.e. $\text{Q}_3\text{Q}_2\text{Q}_1\text{Q}_0=0110,$ then after the next positive edge of the clock signal the new state will be (in decimal)? (the flip-flops are positive edge triggered)

For the circuit in the figure below, if the current state $\text{Q}_3\text{Q}_2\text{Q}_1\text{Q}_0$ is $6$ (in decimal) i.e. $\text{Q}_3\text{Q}_2\text{Q}_1\text{Q}_0=01...

Mahanth Yalla

590 views

Mahanth Yalla answered Jan 30

4 votes

2 answers

31

GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 60
You are asked to implement the following four functions with half-adders: ... of half-adders required to implement all four functions simultaneously? (You are not allowed to use any other logic element but half-adder)

You are asked to implement the following four functions with half-adders:$$\begin{aligned}& \mathrm{f}_1=A \oplus B \oplus C \\& \mathrm{f}_2=A^{\prime} B C+A B^{\prime} ...

Mahanth Yalla

537 views

Mahanth Yalla answered Jan 29

5 votes

1 answer

32

GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 29
In two's complement, what is the minimum number of bits needed to represent the numbers $-1$ and the number $1$ respectively? $1$ and $2$ $2$ and $2$ $2$ and $1$ $1$ and $1$

In two's complement, what is the minimum number of bits needed to represent the numbers $-1$ and the number $1$ respectively?$1$ and $2$$2$ and $2$$2$ and $1$$1$ and $1$

Deepak Poonia

534 views

Deepak Poonia answered Jan 28

3 votes

1 answer

33

GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 25
A garage door opens if it ever sees the password $011$ in a transmission. More formally, this FSM takes a bitstring consisting of $\text{0's}$ and $\text{1's}$ as its input, and continually outputs $\text{0's}$ until it sees the substring $011,$ ... Arrow $1 - (0/0)$ Arrow $3 - (1/0)$ Arrow $4 - (1/0)$ Arrow $5 - (1/1)$

A garage door opens if it ever sees the password $011$ in a transmission. More formally, this FSM takes a bitstring consisting of $\text{0's}$ and $\text{1's}$ as its inp...

GO Classes

393 views

GO Classes answered Jan 28

4 votes

1 answer

34

GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 26
The figure below represents the Karnaugh map for a function $\text{F(A,B,C,D).}$ Note, $\text{ X'}$ stands for don't care. The simplified logical expression in the sum-of-products (SOP) form (i.e., the minimum number of ... can be converted into a circuit implementation using only NAND gates, which is shown in: a b c d

The figure below represents the Karnaugh map for a function $\text{F(A,B,C,D).}$ Note, $\text{‘X’}$ stands for don’t care.The simplified logical expression in the s...

GO Classes

390 views

GO Classes answered Jan 28

2 votes

2 answers

35

GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 39
The circuit shown below is designed using two multiplexers. This circuit is equivalent to: a positive edge triggered $\mathrm{T}$ flip flop a negative edge triggered $\mathrm{T}$ flip flop a negative edge triggered $\text{D}$ flip flop a positive edge triggered $\mathrm{D}$ flip flop

The circuit shown below is designed using two multiplexers.This circuit is equivalent to:a positive edge triggered $\mathrm{T}$ flip flopa negative edge triggered $\mathr...

Shreyas16

906 views

Shreyas16 answered Jan 27

5 votes

2 answers

36

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 53
Consider the following $4$-bit adder circuit. Note, $\text{C}_0$ is carry in and $\text{C}_4$ is carry out for the $4$-bit adder. The given circuit operates on $\text{2's}$ ... $\text{S}=1$

Consider the following $4$-bit adder circuit.Note, $\text{C}_0$ is carry in and $\text{C}_4$ is carry out for the $4$-bit adder. The given circuit operates on $\text{2's}...

RAGING_THUNDER_511

753 views

RAGING_THUNDER_511 answered Jan 26

1 votes

0 answers

37

ripple counter
In a ripple counter, the state whose output has a frequency equal to 1/8th that of the clock signal applied to the first stage, also has an output periodicity equal to 1/8th that of the output signal obtained from the last stage. The counter is

In a ripple counter, the state whose output has a frequency equal to 1/8th that of the clock signal applied to the first stage, also has an output periodicity equal to 1/...

BhuvanBhasutkar

174 views

BhuvanBhasutkar asked Jan 23

2 votes

1 answer

38

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 51
We would like to use a $\text{T}$ flip-flop and design a circuit that works like a $\text{J-K}$ flip-flop. The simplified input to the $\text{T}$ flip-flop should be: $\mathrm{T}=\mathrm{J}=\mathrm{K}$ $\text{T}=\text{JQ}^{\prime}+\text{K}^{\prime} Q$ $\text{T}=\text{JQ}^{\prime}+K Q$ $\text{T}=\text{JQ}+\text{KQ}'$

We would like to use a $\text{T}$ flip-flop and design a circuit that works like a $\text{J-K}$ flip-flop. The simplified input to the $\text{T}$ flip-flop should be:$\ma...

siddharth2109

500 views

siddharth2109 answered Jan 22

3 votes

1 answer

39

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 52
Consider the sequential circuit shown below. Consider the following state assignment: $\text{A}$ stands for $\text{Q = 0, B}$ stands for $\text{Q = 1}.$ The state transition diagram for the circuit above is shown in: a b c d

Consider the sequential circuit shown below.Consider the following state assignment: $\text{A}$ stands for $\text{Q = 0, B}$ stands for $\text{Q = 1}.$ The state transiti...

krishnajsw

701 views

krishnajsw answered Jan 22

4 votes

1 answer

40

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 21
How many $\text{4-to-1}$ multiplexers are needed to implement a $\text{64-to-1}$ multiplexer?

How many $\text{4-to-1}$ multiplexers are needed to implement a $\text{64-to-1}$ multiplexer?

GO Classes

446 views

GO Classes asked Jan 21

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