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Recent questions and answers in Digital Logic
0
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1
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1
2421 code
in 2421 code for 5 is 1011 why not 0101 ?????????
Turban_trap
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Digital Logic
3 days
ago
by
Turban_trap
1.9k
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34
votes
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2
GATE IT 2005 | Question: 48
The circuit shown below implements a $\text{2-input}$ NOR gate using two $2-4$ MUX (control signal $1$ selects the upper input). What are the values of signals $x, y$ and $z$? $1, 0, B$ $1, 0, A$ $0, 1, B$ $0, 1, A$
ANIL Kr.
answered
in
Digital Logic
Feb 23
by
ANIL Kr.
7.5k
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gateit-2005
digital-logic
normal
multiplexer
1
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3
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3
GATE CSE 2024 | Set 1 | Question: 54
Consider a digital logic circuit consisting of three $2$-to-$1$ multiplexers $\text{M1, M2}$, and $\text{M3}$ as shown below. $\mathrm{X} 1$ and $\mathrm{X} 2$ are inputs of $\mathrm{M} 1$. $\text{X3}$ and $\text{X4}$ are inputs ... the number of combinations of $\mathrm{A}, \mathrm{B}, \mathrm{C}$ that give the output $\mathbf{Y}=\mathbf{1}$ is ____________.
GauravRajpurohit
answered
in
Digital Logic
Feb 18
by
GauravRajpurohit
1.8k
views
gatecse2024-set1
numerical-answers
digital-logic
multiplexer
2
votes
5
answers
4
GATE CSE 2024 | Set 1 | Question: 3
Consider a system that uses $5$ bits for representing signed integers in $2$ 's complement format. In this system, two integers $A$ and $B$ are represented as $A$=$01010$ and $B$=$11010$. Which one of the following operations will result in either an arithmetic overflow or an arithmetic underflow? $A+B$ $A-B$ $B-A$ $2 * B$
Psy Duck
answered
in
Digital Logic
Feb 17
by
Psy Duck
3.3k
views
gatecse2024-set1
digital-logic
2
votes
1
answer
5
GATE CSE 2024 | Set 1 | Question: 18
Consider the circuit shown below where the gates may have propagation delays. Assume that all signal transitions occur instantaneously and that wires have no delays. Which of the following statements about the circuit is/are CORRECT? With no propagation ... , the output $Y$ can have a transient logic Zero after $X$ transitions from logic One to logic Zero
phaniphani
answered
in
Digital Logic
Feb 17
by
phaniphani
2.0k
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gatecse2024-set1
multiple-selects
digital-logic
0
votes
2
answers
6
GATE CSE 2024 | Set 1 | Question: 37
Consider a Boolean expression given by $\text{F(X, Y, Z)}=\sum(3,5,6,7)$. Which of the following statements is/are CORRECT? $\text{F(X, Y, Z)}=\Pi(0,1,2,4)$ $\text{F(X, Y, Z)=X Y+Y Z+X Z}$ $\text{F(X, Y, Z)}$ is independent of input $\text{Y}$ $\text{F(X, Y, Z)}$ is independent of input $\text{X}$
Hira Thakur
answered
in
Digital Logic
Feb 17
by
Hira Thakur
1.7k
views
gatecse2024-set1
multiple-selects
digital-logic
2
votes
2
answers
7
GATE CSE 2024 | Set 2 | Question: 20
For a Boolean variable $x$, which of the following statements is/are FALSE? $x .1=x$ $x+1=x$ $x \cdot x=0$ $x+\bar{x}=1$
Hira Thakur
answered
in
Digital Logic
Feb 17
by
Hira Thakur
1.8k
views
gatecse2024-set2
digital-logic
boolean-algebra
easy
multiple-selects
0
votes
1
answer
8
GATE CSE 2024 | Set 2 | Question: 4
The format of a single-precision floating-point number as per the $\text{IEEE 754}$ standard is: Sign Exponent Mantissa $(1 \mathrm{bit})$ $(8 \mathrm{bits})$ $(23 \mathrm{bits})$ Choose the largest floating- ... $0$ $11111111$ $11111111111111111111111$ Sign Exponent Mantissa $0$ $01111111$ $00000000000000000000000$
supreetshukla
answered
in
Digital Logic
Feb 17
by
supreetshukla
2.2k
views
gatecse2024-set2
digital-logic
number-representation
ieee-representation
2
votes
1
answer
9
GATE CSE 2024 | Set 2 | Question: 40
Consider $4$-variable functions $f 1, f 2, f 3, f 4$ expressed in sum-of-minterms form as given below. \[ \begin{array}{l} f 1=\sum(0,2,3,5,7,8,11,13) \\ f 2=\sum(1,3,5,7,11,13,15) \\ f 3=\sum(0,1,4,11) \\ f 4=\sum(0,2,6,13) \end{array} \] With ... $\boldsymbol{Y}=\sum(0,1,2,3,4,5,6,7)$ $\boldsymbol{Y}=\Pi(8,9,10,11,12,13,14,15)$
Hira Thakur
answered
in
Digital Logic
Feb 17
by
Hira Thakur
1.5k
views
gatecse2024-set2
digital-logic
canonical-normal-form
multiple-selects
1
vote
1
answer
10
GATE CSE 2024 | Set 2 | Question: 39
Which of the following is/are EQUAL to $224$ in radix - $5$ (i.e., base - $5$) notation? $64$ in radix -10 $100$ in radix -8 $50$ in radix -16 $121$ in radix -7
Hira Thakur
answered
in
Digital Logic
Feb 17
by
Hira Thakur
1.5k
views
gatecse2024-set2
digital-logic
number-representation
multiple-selects
3
votes
1
answer
11
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 29
The largest positive number in 2's complement format represented with 8-bits is: $(\mathrm{FF})_{16}$ $(128)_{10}$ $(777)_8$ $(01111111)_2$
TusharRana
answered
in
Digital Logic
Feb 13
by
TusharRana
411
views
goclasses2024-mockgate-14
digital-logic
number-representation
1-mark
35
votes
5
answers
12
GATE CSE 2015 Set 3 | Question: 35
Consider the equation $(43)_x = (y3)_8$ where $x$ and $y$ are unknown. The number of possible solutions is _____
rajveer43
answered
in
Digital Logic
Feb 8
by
rajveer43
9.8k
views
gatecse-2015-set3
digital-logic
number-representation
normal
numerical-answers
0
votes
1
answer
13
self doubts
how to simplify this boolean function i tend to get confuse on this given problem F(a,b,c)=(AB+AC)'+A'B'C
Mrityudoot
answered
in
Digital Logic
Feb 7
by
Mrityudoot
185
views
4
votes
1
answer
14
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 30
Consider the function $f\left(x_1, x_2, x_3\right)=x_1 \cdot x_2 \cdot x_3+\bar{x}_1 \cdot \bar{x}_2 \cdot \bar{x}_3+\bar{x}_1 \cdot x_2 \cdot \bar{x}_3+\bar{x}_1 \cdot x_2 \cdot x_3$, what is the product of sum(POS) expression ...
squirrel69
answered
in
Digital Logic
Feb 6
by
squirrel69
410
views
goclasses2024-mockgate-14
digital-logic
boolean-algebra
1-mark
2
votes
1
answer
15
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 59
Consider the shift register circuit shown in below figure. Assume that $\mathbf{I}_3 \mathbf{I}_2 \mathbf{I}_1 \mathbf{I}_0=0101$ has been loaded in the 4-bit register using the parallel load mechanism (i.e., shift=0 ... consecutive positive edges of the clock signal we need to keep shift=1 such that zero detect is activated to a 1?
TotalBiscuit
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in
Digital Logic
Feb 6
by
TotalBiscuit
431
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goclasses2024-mockgate-14
numerical-answers
digital-logic
sequential-circuit
shift-registers
2-marks
5
votes
2
answers
16
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 61
According to the IEEE standard, a 32-bit, single-precision, floating-point number $N$ is defined to be $ N=(-1)^S \times 1 . F \times 2^{E-127} $ where $S$ is the sign bit, $F$ the fractional mantissa, and $E$ the biased exponent. A floating- ... $\left(1-2^{-23}\right) * 2^{128}$ $\left(1+\left(1-2^{-23}\right)\right) * 2^{128}$
Shreyas16
answered
in
Digital Logic
Feb 6
by
Shreyas16
504
views
goclasses2024-mockgate-14
digital-logic
number-representation
ieee-representation
floating-point-representation
2-marks
2
votes
1
answer
17
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 28
Consider function $\mathbf{G}(\mathbf{A}, \mathbf{B}, \mathbf{C})=\mathbf{A B}+\mathbf{B C}$. Let $\mathbf{F}(\mathbf{A}, \mathbf{B}, \mathbf{C})$ ... input to a 2-to-1 multiplexer. The correct implementation of $\mathbf{F}(\mathbf{A}, \mathbf{B}, \mathbf{C})$ is shown in:
keshav_18
answered
in
Digital Logic
Feb 6
by
keshav_18
424
views
goclasses2024-mockgate-14
digital-logic
combinational-circuit
multiplexer
1-mark
3
votes
0
answers
18
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 60
The logic circuit above is used to compare two unsigned 2-bit numbers, $X_1 X_0=X$ and $Y_1 Y_0=Y$, where $X_0$ and $Y_0$ are the least significant bits. (A small circle on any line in a logic diagram indicates logical NOT.) Which of the following always makes the output $Z$ have the value 1? $X\gt Y$ $X\lt Y$ $X=Y$ $X \neq Y$
GO Classes
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in
Digital Logic
Feb 5
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GO Classes
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goclasses2024-mockgate-14
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2-marks
0
votes
1
answer
19
how is the minimum number of NOR gates required is 5?
Mrityudoot
answered
in
Digital Logic
Jan 30
by
Mrityudoot
145
views
digital-logic
made-easy-test-series
2
votes
3
answers
20
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 59
For the circuit in the figure below, if the current state $\text{Q}_3\text{Q}_2\text{Q}_1\text{Q}_0$ is $6$ (in decimal) i.e. $\text{Q}_3\text{Q}_2\text{Q}_1\text{Q}_0=0110,$ then after the next positive edge of the clock signal the new state will be (in decimal)? (the flip-flops are positive edge triggered)
Mahanth Yalla
answered
in
Digital Logic
Jan 30
by
Mahanth Yalla
473
views
goclasses2024-mockgate-13
goclasses
numerical-answers
digital-logic
sequential-circuit
digital-counter
2-marks
4
votes
2
answers
21
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 60
You are asked to implement the following four functions with half-adders: ... of half-adders required to implement all four functions simultaneously? (You are not allowed to use any other logic element but half-adder)
Mahanth Yalla
answered
in
Digital Logic
Jan 29
by
Mahanth Yalla
438
views
goclasses2024-mockgate-13
goclasses
numerical-answers
digital-logic
combinational-circuit
adder
2-marks
2
votes
1
answer
22
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 27
What statement is correct for $f(A, B)$ in the following circuit? $f(A, B)=\overline{\overline{A \cdot B} \cdot(A+B)}$ when Control $=1$ $f(A, B)=A \cdot B$ when Control $=0$ $f(A, B)=\overline{A}+\overline{B}$ when Control $=1$ $f(A, B)=\overline{A} \cdot \overline{B}$ when Control $=0$
SankarVinayak
answered
in
Digital Logic
Jan 29
by
SankarVinayak
295
views
goclasses2024-mockgate-13
goclasses
digital-logic
digital-circuits
multiple-selects
1-mark
5
votes
1
answer
23
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 29
In two's complement, what is the minimum number of bits needed to represent the numbers $-1$ and the number $1$ respectively? $1$ and $2$ $2$ and $2$ $2$ and $1$ $1$ and $1$
Deepak Poonia
answered
in
Digital Logic
Jan 29
by
Deepak Poonia
445
views
goclasses2024-mockgate-13
goclasses
digital-logic
number-representation
1-mark
3
votes
1
answer
24
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 25
A garage door opens if it ever sees the password $011$ in a transmission. More formally, this FSM takes a bitstring consisting of $\text{0's}$ and $\text{1's}$ as its input, and continually outputs $\text{0's}$ until it sees the substring $011,$ after which ... ? Arrow $1 - (0/0)$ Arrow $3 - (1/0)$ Arrow $4 - (1/0)$ Arrow $5 - (1/1)$
GO Classes
answered
in
Digital Logic
Jan 28
by
GO Classes
323
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goclasses2024-mockgate-13
goclasses
digital-logic
sequential-circuit
finite-automata
multiple-selects
1-mark
4
votes
1
answer
25
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 26
The figure below represents the Karnaugh map for a function $\text{F(A,B,C,D).}$ Note, $\text{ X'}$ stands for don't care. The simplified logical expression in the sum-of-products (SOP) form (i.e., the minimum number of ... can be converted into a circuit implementation using only NAND gates, which is shown in: a b c d
GO Classes
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in
Digital Logic
Jan 28
by
GO Classes
295
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goclasses2024-mockgate-13
goclasses
digital-logic
boolean-algebra
k-map
1-mark
2
votes
2
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26
GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 39
The circuit shown below is designed using two multiplexers. This circuit is equivalent to: a positive edge triggered $\mathrm{T}$ flip flop a negative edge triggered $\mathrm{T}$ flip flop a negative edge triggered $\text{D}$ flip flop a positive edge triggered $\mathrm{D}$ flip flop
Shreyas16
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in
Digital Logic
Jan 27
by
Shreyas16
739
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goclasses2024-mockgate-11
goclasses
digital-logic
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flip-flop
2-marks
5
votes
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27
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 53
Consider the following $4$-bit adder circuit. Note, $\text{C}_0$ is carry in and $\text{C}_4$ is carry out for the $4$-bit adder. The given circuit operates on $\text{2's}$ ... $\text{S}=1$
RAGING_THUNDER_511
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Digital Logic
Jan 26
by
RAGING_THUNDER_511
593
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28
ripple counter
In a ripple counter, the state whose output has a frequency equal to 1/8th that of the clock signal applied to the first stage, also has an output periodicity equal to 1/8th that of the output signal obtained from the last stage. The counter is
BhuvanBhasutkar
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in
Digital Logic
Jan 23
by
BhuvanBhasutkar
119
views
2
votes
1
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29
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 51
We would like to use a $\text{T}$ flip-flop and design a circuit that works like a $\text{J-K}$ flip-flop. The simplified input to the $\text{T}$ flip-flop should be: $\mathrm{T}=\mathrm{J}=\mathrm{K}$ $\text{T}=\text{JQ}^{\prime}+\text{K}^{\prime} Q$ $\text{T}=\text{JQ}^{\prime}+K Q$ $\text{T}=\text{JQ}+\text{KQ}'$
siddharth2109
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in
Digital Logic
Jan 22
by
siddharth2109
428
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goclasses2024-mockgate-12
goclasses
digital-logic
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flip-flop
2-marks
3
votes
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30
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 52
Consider the sequential circuit shown below. Consider the following state assignment: $\text{A}$ stands for $\text{Q = 0, B}$ stands for $\text{Q = 1}.$ The state transition diagram for the circuit above is shown in: a b c d
krishnajsw
answered
in
Digital Logic
Jan 22
by
krishnajsw
571
views
goclasses2024-mockgate-12
goclasses
digital-logic
sequential-circuit
flip-flop
2-marks
2
votes
3
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31
GO Classes Test Series 2023 | Digital Logic | Test 2 | Question: 21
A combinational logic circuit takes a $4$-bit unsigned binary integer number at its inputs labeled $\mathrm{D}_{3}, \mathrm{D}_{2}, \mathrm{D}_{1}$ and $\mathrm{D}_{0}$, where $\mathrm{D}_{3}$ is the most ... $0$ otherwise. How many prime implicants does $S$ have which are not essential prime implicants?
Shubham_cse
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in
Digital Logic
Jan 21
by
Shubham_cse
203
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goclasses2024-dl-2-weekly-quiz
numerical-answers
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digital-circuits
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2
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32
GO Classes Test Series 2023 | Digital Logic | Test 2 | Question: 13
The $8$ to $3$ Encoder or Octal to Binary encoder consists of $8$ inputs : $O_{7}$ to $\mathrm{O}_{0}$ and $3$ outputs $: B_{2}, B_{1}$ and $\mathrm{B}_{0}$. Each input line corresponds to each octal digit and three outputs ... $B_{1}$ and $B_{2}$ are Correct $B_{0}$ and $B_{1}$ are Correct All of them are Correct
Shubham_cse
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Digital Logic
Jan 21
by
Shubham_cse
260
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goclasses
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3
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33
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 21
How many $\text{4-to-1}$ multiplexers are needed to implement a $\text{64-to-1}$ multiplexer?
Abbas am
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Digital Logic
Jan 21
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Abbas am
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34
GATE CSE 2015 Set 1 | Question: 20
Consider a $4$-bit Johnson counter with an initial value of $0000.$ The counting sequence of this counter is $0, 1, 3, 7, 15, 14, 12, 8, 0$ $0, 1, 3, 5, 7, 9, 11, 13, 15, 0$ $0, 2, 4, 6, 8, 10, 12, 14, 0$ $0, 8, 12, 14, 15, 7, 3, 1, 0$
Ray Tomlinson
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Digital Logic
Jan 21
by
Ray Tomlinson
20.5k
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digital-counter
easy
2
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35
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 22
What is the output for the following circuit? $w=\overline{b} c$ $w=b \oplus c$ $w=\overline{b \oplus c}$ $w=\overline{b}+\overline{c}$
Hira Thakur
answered
in
Digital Logic
Jan 21
by
Hira Thakur
340
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goclasses2024-mockgate-12
goclasses
digital-logic
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1-mark
24
votes
3
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36
GATE CSE 2021 Set 2 | Question: 52
Consider a Boolean function $f(w,x,y,z)$ such that $\begin{array}{lll} f(w,0,0,z) & = & 1 \\ f(1,x,1,z) & =& x+z \\ f(w,1,y,z) & = & wz +y \end{array}$The number of literals in the minimal sum-of-products expression of $f$ is _________
phaniphani
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in
Digital Logic
Jan 21
by
phaniphani
13.1k
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gatecse-2021-set2
digital-logic
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min-sum-of-products-form
numerical-answers
2-marks
53
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2
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37
GATE CSE 2010 | Question: 7
The main memory unit with a capacity of $4$ $\text{megabytes}$ is built using $1\text{M} \times \text{1-bit}$ DRAM chips. Each DRAM chip has $1\text{K}$ rows of cells with $1\text{K}$ cells in each row. The time taken for a single ... in the memory unit is $100$ nanoseconds $100\times 2^{10}$ nanoseconds $100\times 2^{20}$ nanoseconds $3200\times 2^{20}$ nanoseconds
palak bafna
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Digital Logic
Jan 16
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palak bafna
18.7k
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0
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0
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38
Byjus Mock Test
I am unable to understand the language of the question , can someone help me??
Dadu
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Jan 15
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Dadu
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39
GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 16
Which one of the following options is CORRECT for the given logic circuit? $P=1, Q=1 ; X=0$ $P=1, Q=0 ; X=1$ $P=0, Q=1 ; X=0$ $P=0, Q=0 ; X=1$
GO Classes
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Jan 13
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GO Classes
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