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Recent questions and answers in Digital Logic

1 vote
3 answers
1
Consider a $3$-bit counter, designed using $T$ flip-flops, as shown below: Assuming the initial state of the counter given by $\text{PQR}$ as $000$, what are the next three states? $011,101,000$ $001,010,111$ $011,101,111$ $001,010,000$
answered Feb 27 in Digital Logic Harshq 216 views
0 votes
4 answers
2
Consider the following representation of a number in $\text{IEEE 754}$ single-precision floating point format with a bias of $127$. $S: 1\quad\quad E:\; 10000001\quad\quad F:\;11110000000000000000000$ Here, $S, \;E$ and $F$ denote ... components of the floating point representation. The decimal value corresponding to the above representation (rounded to $2$ decimal places) is ____________.
answered Feb 27 in Digital Logic Harshq 234 views
0 votes
4 answers
3
1 vote
2 answers
4
The format of the single-precision floating point representation of a real number as per the $\text{IEEE 754}$ ... $=00000000$ and mantissa $=0000000000000000000000001$ exponent $=00000001$ and mantissa $=0000000000000000000000000$ exponent $=00000001$ and mantissa $=0000000000000000000000001$
answered Feb 26 in Digital Logic harish3598 366 views
0 votes
4 answers
5
If the numerical value of a $2$-byte unsigned integer on a little endian computer is $255$ more than that on a big endian computer, which of the following choices represent(s) the unsigned integer on a little endian computer? $0\text{x}6665$ $0\text{x} 0001$ $0\text{x} 4243$ $0\text{x} 0100$
answered Feb 23 in Digital Logic HitechGa 1.8k views
1 vote
3 answers
6
2 votes
1 answer
7
Consider the following Boolean expression. $F=(X+Y+Z)(\overline X +Y)(\overline Y +Z)$ Which of the following Boolean expressions is/are equivalent to $\overline F$ (complement of $F$)? $(\overline X +\overline Y +\overline Z)(X+\overline Y)(Y+\overline Z)$ $X\overline Y + \overline Z$ $(X+\overline Z)(\overline Y +\overline Z)$ $X\overline Y +Y\overline Z + \overline X \overline Y \overline Z$
answered Feb 18 in Digital Logic Bhargav D Dave 6 213 views
0 votes
1 answer
9
Consider a Boolean function $f(w,x,y,z)$ such that $\begin{array}{lll} f(w,0,0,z) & = & 1 \\ f(1,x,1,z) & =& x+z \\ f(w,1,y,z) & = & wz +y \end{array}$ The number of literals in the minimal sum-of-products expression of $f$ is _________
answered Feb 18 in Digital Logic zxy123 335 views
24 votes
5 answers
10
1 vote
2 answers
11
0 votes
2 answers
13
Please Explain the Rule to find number of additions and subtractions required for multiplication of two given numbers.
answered Feb 15 in Digital Logic adeemajain 550 views
0 votes
1 answer
14
1) In Booth's bit-pair recording technique how to multiply a multiplicand with 2? 2) In booth's algorithm for multiplication/Booth's bit-pair recording of multipliers, the sign bit extension of the multiplicand i.e. we must extend the sign-bit value of the multiplicand to the left ... +2 I don't know Also, why is the sign bit extended? Will we get the correct answer if we don't extend sign bit?
answered Feb 15 in Digital Logic adeemajain 1.1k views
1 vote
2 answers
16
What is the Booth’s coding in 8-bits for an integer (-86)?
answered Feb 15 in Digital Logic adeemajain 1.9k views
1 vote
2 answers
17
The characteristic equation of a $\text{T}$ flip-flop is : $Q_{n+1}=T\overline Q_n+\overline T Q_n$ $Q_{n+1}=T+Q_n$ $Q_{n+1}=TQ_n$ $Q_{n+1}=\overline T$\overline Q_n$ The symbols used have the usual meaning.
answered Feb 15 in Digital Logic Hira Thakur 124 views
0 votes
3 answers
18
In $\text{RS}$ flip-flop, the output of the flip-flop at time $(t+1)$ same as the output at time $t$, after the occurrence of a clock pulse if : $S=R=1$ $S=0, R=1$ $S=2, R=0$ $S=R=0$
answered Feb 12 in Digital Logic arnabbarui3 515 views
65 votes
4 answers
19
Minimum No of Gates NAND/NOR Ex-OR Ex-Nor Half Adder Half Subtractor Full Adder Full Subtractor NAND ? ? ? ? ? ? NOR ? ? ? ? ? ?
answered Feb 10 in Digital Logic ijnuhb 67.3k views
62 votes
8 answers
20
Consider a carry look ahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is $\Theta (1)$ $\Theta (\log(n))$ $\Theta (\sqrt{n})$ $\Theta (n)$)
answered Feb 9 in Digital Logic goldenface 17.2k views
17 votes
7 answers
21
Consider three $4$-variable functions $f_1, f_2$, and $f_3$, which are expressed in sum-of-minterms as $f_1=\Sigma(0,2,5,8,14),$ $f_2=\Sigma(2,3,6,8,14,15),$ $f_3=\Sigma (2,7,11,14)$ For the following circuit with one AND gate and one XOR gate the output function $f$ can be expressed as: $\Sigma(7,8,11)$ $\Sigma (2,7,8,11,14)$ $\Sigma (2,14)$ $\Sigma (0,2,3,5,6,7,8,11,14,15)$
answered Feb 8 in Digital Logic varunrajarathnam 6.8k views
1 vote
3 answers
22
0 votes
2 answers
23
If the input $\text{J}$ is connected through $\text{K}$ input of $\text{J-K}$, then flip-flop will behave as a D type flip-flop T type flip-flop S-R flip-flop Toggle switch
answered Feb 6 in Digital Logic anjli 132 views
0 votes
3 answers
24
If a clock with time period $“T”$ is used with $n$ stage shift register, then output of final stage will be delayed by $nT$ sec $(n-1)T$ sec $n/T$ sec $(2n-1)T$ sec
answered Feb 6 in Digital Logic anjli 211 views
0 votes
2 answers
25
A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is $\text{S-R}$ Flip-flop with inputs $X = R$ and $Y=S$ $\text{S-R}$ Flip-flop with inputs $X = S$ and $Y=R$ $\text{J-K}$ Flip-flop with inputs $X = J$ and $Y=K$ $\text{J-K}$ Flip-flop with inputs $X = K$ and $Y=J$
answered Feb 6 in Digital Logic anjli 258 views
0 votes
4 answers
26
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
answered Feb 6 in Digital Logic anjli 298 views
1 vote
2 answers
27
A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is $\text{S-R}$ Flip-flop with inputs $X = R$ and $Y=S$ $\text{S-R}$ Flip-flop with inputs $X = S$ and $Y=R$ $\text{J-K}$ Flip-flop with inputs $X = J$ and $Y=K$ $\text{J-K}$ Flip-flop with inputs $X = K$ and $Y=J$
answered Feb 6 in Digital Logic anjli 957 views
0 votes
1 answer
28
The period of a signal is $100$ ms, then the frequency of this signal in kilohertz is ______ $10$ $10^{-1}$ $10^{-2}$ $10^{-3}$
asked Nov 20, 2020 in Digital Logic jothee 157 views
0 votes
3 answers
29
Simplified expression/s for following Boolean function $F(A,B,C,D)=\Sigma(0,1,2,3,6,12,13,14,15)$ is/are $A’B’+AB+A’C’D’$ $A’B’+AB+A’CD’$ $A’B’+AB+BC’D’$ $A’B’+AB+BCD’$ Choose the correct answer from the options given below: $(a)$ only $(b)$ only $(a)$ and $(b)$ only $(b)$ and $(d)$ only
asked Nov 20, 2020 in Digital Logic jothee 193 views
1 vote
1 answer
30
is given ans correct ?
asked Aug 31, 2020 in Digital Logic Sanjay Sharma 446 views
0 votes
0 answers
31
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
asked Aug 28, 2020 in Digital Logic Lakshman Patel RJIT 148 views
0 votes
1 answer
32
1 vote
1 answer
33
A sequential circuit outputs a $\text{ONE}$ when an even number$(>0)$ of one’s are input; otherwise the output is $\text{ZERO}.$ The minimum number of states required is $0$ $1$ $2$ $3$
asked Apr 2, 2020 in Digital Logic Lakshman Patel RJIT 277 views
0 votes
1 answer
34
0 votes
1 answer
35
Which of the following conditions must be met to avoid race around problem? $\Delta t< t_{p}< T$ $T>\Delta t> t_{p}$ $2t_{p}< \Delta t< T$ none of these
asked Apr 2, 2020 in Digital Logic Lakshman Patel RJIT 136 views
0 votes
1 answer
36
The excess $3$ code is also called cyclic redundancy code weighted code self complimenting code algebraic code
asked Apr 2, 2020 in Digital Logic Lakshman Patel RJIT 132 views
0 votes
2 answers
37
1 vote
1 answer
38
0 votes
1 answer
39
In a ripple counter using edge-triggered $JK$ flip-flops, the pulse input is applied to Clock input of all flip-flops $J$ and $K$ input of one flip-flop $J$ and $K$ input of all flip-flops Clock input of one flip-flop
asked Apr 1, 2020 in Digital Logic Lakshman Patel RJIT 127 views
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