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Recent questions and answers in Digital Logic
0
votes
1
answer
1
igate test series
If a Boolean function is having cyclic prime implicants K-map, then the number of minimal forms for function is________
afroze
answered
in
Digital Logic
3 hours
ago
by
afroze
10
views
test-series
k-map
prime-implicants
boolean-algebra
13
votes
5
answers
2
Simplified Boolean expression for A'BC+AB'C'+A'B'C'+AB'C+ABC
Simplified Boolean expression for A'BC+AB'C'+A'B'C'+AB'C+ABC A . AB B . B'C C . AB+(A'+AB')C D . AB'+BC+B'C'
D Trump
answered
in
Digital Logic
4 days
ago
by
D Trump
54.9k
views
digital-logic
boolean-algebra
0
votes
2
answers
3
UPPCL AE 2018:22
If we decide to stay away from $\text{IEEE 754}$ format by making our Exponent field $10$ bits wide and our Mantissa field $21$ bits wide, then which of the following statement is $\text{TRUE}$? It will provide less precision as there will be fewer Mantissa bits It will provide more precision as there will be fewer Mantissa bits None of the above It will not change the precision
duttabhishek0
answered
in
Digital Logic
5 days
ago
by
duttabhishek0
156
views
uppcl2018
digital-logic
number-representation
ieee-representation
0
votes
0
answers
4
Digital Logic
To design n input NOR gate, the number of 2 input NOR gate =2n - 3. Somebody please verify and explain with example ( diagram).
GateOverflow04
asked
in
Digital Logic
Sep 22
by
GateOverflow04
33
views
digital-logic
self-doubt
0
votes
0
answers
5
Digital Logic | Doubt
Hamming Distance: We can calculate how much Hamming Distance should be there so that we can correct any wrong bit Hamming Code: By Hamming Code we can correct any wrong bit. Questions: 1] Are they both different techniques or there is relation ... Hamming Distance in any two numbers). 2] Why should anybody use Hamming Code where we can correct error by Hamming Distance?
anupamsworld
asked
in
Digital Logic
Sep 18
by
anupamsworld
28
views
digital-logic
hamming-code
0
votes
1
answer
6
Applied test series question
A 4-bit carry lookahead adder adds two 4-bit numbers. The adder is designed without making use of the EX-OR gates. The propagation delay for all gates is given as 2.4 time units. What will be the overall delay of adder if we assume that inputs ... AND, Or gates. can someone explain me this in a deatiled manner as i am not able to find the appropriate solution for it ?
neel19
answered
in
Digital Logic
Sep 17
by
neel19
75
views
test-series
digital-logic
adder
28
votes
5
answers
7
GATE IT 2005 | Question: 47
$(34.4)_{8} × \left ( 23.4 \right )_{8}$ evaluates to $(1053.6)_{8}$ $(1053.2)_{8}$ $(1024.2)_{8}$ None of these
Dewesh Jha
answered
in
Digital Logic
Sep 14
by
Dewesh Jha
6.0k
views
gateit-2005
digital-logic
number-representation
normal
5
votes
2
answers
8
GATE Overflow | Mock GATE | Test 1 | Question: 25
Consider the function: int fun(int n) { if (n==4) return n; else return 2*fun(n+1); } A MOD-16 ripple counter is holding the count $(1001)_2.$ What will be the count after "$(\text{fun}(2)+15)_{10}$" clock pulses? $(1000)_2$ $(1010)_2$ $(1011)_2$ $(1101)_2$
MANSI_SOMANI
answered
in
Digital Logic
Sep 13
by
MANSI_SOMANI
699
views
go-mockgate-1
digital-logic
ripple-counter-operation
data-structures
recursion
0
votes
1
answer
9
Computer architecture
Represent +42 and -42 in sign-magnitude, 1’s complement and 2’s complement representation. Find the result of 42 - 20 using 2’s complement.
gate_1729
answered
in
Digital Logic
Sep 11
by
gate_1729
56
views
digital-logic
number-representation
20
votes
6
answers
10
GATE CSE 1990 | Question: 5-b
Show with the help of a block diagram how the Boolean function : $f=AB+BC+CA$ can be realised using only a $4:1$ multiplexer.
GateOverflow04
answered
in
Digital Logic
Sep 4
by
GateOverflow04
3.1k
views
gate1990
descriptive
digital-logic
combinational-circuit
multiplexer
0
votes
0
answers
11
Number representation
Does the formula(2^(k-1)) used for caculating the biasing value is correct?
GateOverflow04
asked
in
Digital Logic
Sep 3
by
GateOverflow04
42
views
digital-logic
ace-test-series
number-representation
1
vote
1
answer
12
Various Methods to eliminate Static(0/1) and Dynamic Hazards in Digital Circuits
Hi Guys, What are various techniques to eliminate Static(0/1) and Dynamic Hazards in Digital Circuits ? If you can provide some good reference then it will be really helpful. ping @Puja Mishra, ... , @Anu007, @Hemant Parihar, @ sushmita, @VS @Shweta Nair @Krish__, @Ashwin Kulkarni @reena_kandari and @srestha ji.
rsansiya111
answered
in
Digital Logic
Sep 1
by
rsansiya111
190
views
digital-circuits
hazards
39
votes
5
answers
13
GATE CSE 1996 | Question: 2.23
Consider the following state table for a sequential machine. The number of states in the minimized machine will be ... $4$ $3$ $2$ $1$
manikantsharma
answered
in
Digital Logic
Aug 26
by
manikantsharma
9.7k
views
gate1996
normal
finite-automata
1
vote
1
answer
14
ISI2020-PCB-CS: 8.1
Simplify the following Boolean function in product-of-sums form: $ F(A, B, C, D)=\sum(0,1,2,5,8,9,10) . $
[ Jiren ]
answered
in
Digital Logic
Aug 25
by
[ Jiren ]
65
views
isi2020-pcb-cs
descriptive
digital-logic
boolean-algebra
0
votes
0
answers
15
#gate #digital logic #neutral function #derivation
How formula of neutral function is derived? I get that it has equal number of max and min terms but didnt get derivation
Aditi Thakur
asked
in
Digital Logic
Aug 24
by
Aditi Thakur
70
views
digital-logic
neutral-function
0
votes
0
answers
16
Made easy 2022 Test Series
Please Explain How to Solve this type question in detail if any source Please share.
Amit Mehta
asked
in
Digital Logic
Aug 9
by
Amit Mehta
108
views
digital-logic
0
votes
0
answers
17
ISI2020-PCB-CS: 10
Suppose instead of a decoder with $n$ input bits ( $n$ is even) to access a memory of size $2^{n}$, one uses two decoders of input sizes $k$ bits and $(n-k)$ bits. Explain how these two decoders can be used to access the ... address decoding time. Justify your answer. Assume that the time complexity of the decoder is measured by the number of output lines of that decoder.
Lakshman Patel RJIT
asked
in
Digital Logic
Aug 8
by
Lakshman Patel RJIT
22
views
isi2020-pcb-cs
digital-logic
combinational-circuit
decoder
descriptive
0
votes
1
answer
18
[email protected]
2023 Test Series
Please explain
JAINchiNMay
answered
in
Digital Logic
Aug 6
by
JAINchiNMay
111
views
sequential-circuit
28
votes
5
answers
19
GATE CSE 2002 | Question: 7
Express the function $f(x,y,z) = xy' + yz'$ with only one complement operation and one or more AND/OR operations. Draw the logic circuit implementing the expression obtained, using a single NOT gate and one or more AND/OR gates. ... (without expressing its switching function) into an equivalent logic circuit that employs only $6$ NAND gates each with $2$-inputs.
svas7246
answered
in
Digital Logic
Aug 4
by
svas7246
4.7k
views
gatecse-2002
digital-logic
normal
descriptive
digital-circuits
0
votes
0
answers
20
Digital Logic - Gray Code Representation
Hi, Can someone please tell if gray code representation can also work for negative binary number? I’ve seen examples of gray code for only positive binary number not sure about negative , can someone pls clear the doubt ?
krish71
asked
in
Digital Logic
Aug 1
by
krish71
79
views
digital-logic
binary-codes
general-topic-doubt
33
votes
2
answers
21
GATE CSE 1990 | Question: 1-i
Fill in the blanks: In the two bit full-adder/subtractor unit shown in below figure, when the switch is in position $2$ ___________ using _________ arithmetic.
svas7246
answered
in
Digital Logic
Aug 1
by
svas7246
4.6k
views
gate1990
digital-logic
adder
fill-in-the-blanks
1
vote
1
answer
22
Floating point representation
What is the 16 bits pattern which represent (-13.5) in normalized signed magnitude fraction . S = 1 bit , Exponent = 7 bits , Mantissa = 8 bits . Represent it in hexadecimal also.
Manisha Jaishwal
asked
in
Digital Logic
Jul 16
by
Manisha Jaishwal
148
views
digital-logic
floating-point-representation
0
votes
0
answers
23
Overflow Condition For BCD Arithmetic
How overflow can be detected in BCD Arithmetic?
jomboy
asked
in
Digital Logic
Jul 15
by
jomboy
84
views
digital-logic
combinational-circuit
number-representation
0
votes
1
answer
24
In the equation a(xor)b(xnor)c, does b belong to xor or xnor? what about a(xor)b(xnor)c(xor)d(xnor)e?
jomboy
asked
in
Digital Logic
Jul 14
by
jomboy
144
views
digital-logic
boolean-algebra
1
vote
0
answers
25
digital logic
if the function f(x,y,z) =z[xy’z+xyz’] is implemented using only NOT and OR gates, then the minimum no of gate required? i got 7 my approach is multiply z first term will be zxy’ and 2nd term 0 then using d’morgan law i got 7 but answer is wrong why?
jugnu1337
asked
in
Digital Logic
Jul 10
by
jugnu1337
113
views
digital-logic
1
vote
1
answer
26
digital logic
which is correct? S1 +ve logic AND operation behaves as -ve logic OR operation. S2 fxn f(A,B,C)= AB+BC+CA is a self dual fxn. S2 is true but what is the explanation of S1, what does statement 1 want to say?
jugnu1337
asked
in
Digital Logic
Jul 9
by
jugnu1337
114
views
digital-logic
0
votes
1
answer
27
Let the functions 𝑓1 𝑎, 𝑏, 𝑐 = ∑ 1,2,3,4 and 𝑓2 𝑎, 𝑏, 𝑐 = ∑ 0,2,4,6 .What is 𝑓1 ⊕ 𝑓2?
Shubham_Sanap
asked
in
Digital Logic
Jul 2
by
Shubham_Sanap
164
views
digital-logic
minimization
boolean-algebra
0
votes
0
answers
28
implement binary to excess-3 code converter for 4-bits by preparing the truth table and using karnaugh maps for simplification.
jaybourny
asked
in
Digital Logic
Jun 23
by
jaybourny
85
views
0
votes
0
answers
29
Self-doubt
How many NOR Gates required to realize the given logical expression? Y = (A+C)(A+D')(A+B+C')
Manisha Jaishwal
asked
in
Digital Logic
May 29
by
Manisha Jaishwal
132
views
0
votes
0
answers
30
ISI2021-PCB-C10
Suppose instead of a decoder with n input bits (n is even) to access a memory of size 2^n, one uses two decoders of input sizes k bits and (n-k) bits. Explain how these two decoders can be used to access the memory of size 2^N. ... address decoding time. Justify your answer. Assume that the time complexity of the decoder is measured by the number of output lines of that decoder.
jatin29
asked
in
Digital Logic
May 3
by
jatin29
84
views
digital-logic
decoder
isi
0
votes
1
answer
31
simplify the following logic functionf(ABC)USING k-MAP f(ABC)=(A+B+C') .(A+B'+C')
simplify the following logic functionf(ABC)USING k-MAP f(ABC)=(A+B+C') .(A+B'+C')
saba780
asked
in
Digital Logic
Apr 26
by
saba780
136
views
digital-logic
k-map
logic
functions
0
votes
0
answers
32
How to convert (0.75) base 10 to base 5?
I have tried solving it using the following 0.75 × 5 = 3.75 3.75 × 5 = 18.75 18.75 × 5 = 93.75 But the answer is 0.33333.... I don't understand how did this happen... Please someone explain me
Sk Jamil Ahemad
asked
in
Digital Logic
Mar 23
by
Sk Jamil Ahemad
150
views
digital-logic
3
votes
2
answers
33
GATE CSE 2022 | Question: 8
Let $\text{R1}$ and $\text{R2}$ be two $4 - \text{bit}$ registers that store numbers in $2\text{'s}$ complement form. For the operation $\text{R1 + R2},$ which one of the following values of $\text{R1}$ and $\text{R2}$ ... and $\text{R2 = 1010}$ $\text{R1 = 0011}$ and $\text{R2 = 0100}$ $\text{R1 = 1001}$ and $\text{R2 = 1111}$
Arjun
asked
in
Digital Logic
Feb 15
by
Arjun
1.7k
views
gatecse-2022
digital-logic
number-system
number-representation
4
votes
1
answer
34
GATE CSE 2022 | Question: 30
Consider a digital display system $\text{(DDS)}$ shown in the figure that displays the contents of register $\text{X}.$ A $16 - \text{bit}$ code word is used to load a word in $\text{X},$ either from $\text{S}$ or from $\text{R}.$ $\text{S}$ is a $1024-$ ... $1:10$ de-multiplexer$; \quad \; \;\text{Q}$ is $1:5$ de-multiplexer$; \quad \text{T}$ is $2:1$ multiplexer
Arjun
asked
in
Digital Logic
Feb 15
by
Arjun
906
views
gatecse-2022
digital-logic
combinational-circuit
2
votes
2
answers
35
GATE CSE 2022 | Question: 31
Consider three floating point numbers $\textit{A, B}$ and $\textit{C}$ stored in registers $\text{R}_{\text{A}}, \text{R}_{\text{B}}$ and $\text{R}_{\text{C}},$ respectively as per $\textsf{IEEE-754}$ single precision floating point format. The $\text{32-bit}$ content stored in ... $\textit{A + C} = 0$ $\textit{C = A + B}$ $\textit{B =3C}$ $\textit{(B - C)} > 0$
Arjun
asked
in
Digital Logic
Feb 15
by
Arjun
1.3k
views
gatecse-2022
digital-logic
number-system
number-representation
0
votes
1
answer
36
CSE EXAM 2022
how to solve it
rsansiya111
asked
in
Digital Logic
Feb 12
by
rsansiya111
220
views
digital-logic
0
votes
0
answers
37
(Solved now) Gateoverflow test doubt
In https://gateoverflow.in/356090/Gate-overflow-mock-test-4-56 Aren't asynchronous flip-flops supposed to update output sequentially due to delay? I am getting answer Q0 Q1 as 11 → 00 → 10 → 01 → 11
o
asked
in
Digital Logic
Feb 2
by
o
209
views
gateoverflow
test-series
digital-logic
1
vote
0
answers
38
Morris Morin digital Logic Combinatioal Logic #GATE CSE
Using four half-adders (HDL—see Problem 4.52), (a) Design a full-subtractor circuit incrementer. (A circuit that adds one to a four-bit binary number.) (b)* Design a four-bit combinational decrementer (a circuit that subtracts 1 from a fourbit binary num
Ashit Verma
asked
in
Digital Logic
Jan 29
by
Ashit Verma
145
views
digital-logic
0
votes
1
answer
39
BCD Correction | Made Easy Test Series
why is C incorrect? addition of any two nibbles such as 1000 1000 --------- 0000 Will generate a final carry as 1 0000, which will require the addition of 0110 as 1 0110 to make it correct.
palashbehra5
asked
in
Digital Logic
Jan 29
by
palashbehra5
203
views
bcd
digital-logic
made-easy-test-series
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Recent questions and answers in Digital Logic
Recent Blog Comments
previous years than GATE 2010 paper
Which link are you referring to?
@Arjun I am not able to see GATE 2010...
Should be working now
@Arjun Sir but it is not working. i dont know...