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Recent questions and answers in Digital Logic
+46
votes
9
answers
1
GATE201717
The nbit fixedpoint representation of an unsigned real number $X$ uses $f$ bits for the fraction part. Let $i = nf$. The range of decimal values for $X$ in this representation is $2^{f}$ to $2^{i}$ $2^{f}$ to $\left ( 2^{i}  2^{f} \right )$ 0 to $2^{i}$ 0 to $\left ( 2^{i}  2^{f} \right )$
answered
2 days
ago
in
Digital Logic
by
vipin.gautam1906

6.6k
views
gate20171
digitallogic
numberrepresentation
fixedpointrepresentation
+2
votes
2
answers
2
Logic Gates and switching circuits
The gates G1 & G2 in the figure have propagation delays of 10ns and 20ns respectively. If the input Vi makes an abrupt change from logic 0 to 1 at time t=t0 , then what's the output waveform V0 is ? Also please explain how to handle such kinds of questions of waveform?
answered
4 days
ago
in
Digital Logic
by
adilk2501

468
views
digitallogic
digitalcircuits
+21
votes
4
answers
3
GATE20012.12
Consider the circuit given below with initial state $Q_0=1, Q_1=Q_2=0$. The state of the circuit is given by the value $4Q_2+2Q_1+Q_0$ Which one of the following is correct state sequence of the circuit? $1, 3, 4, 6, 7, 5, 2$ $1, 2, 5, 3, 7, 6, 4$ $1, 2, 7, 3, 5, 6, 4$ $1, 6, 5, 7, 2, 3, 4$
answered
5 days
ago
in
Digital Logic
by
Gaurav Yadav
Junior

3.5k
views
gate2001
digitallogic
normal
synchronousasynchronouscircuits
+2
votes
6
answers
4
NIELIT 2016 MAR Scientist B  Section C: 1
Which of the following logic expression is incorrect? $1\oplus0=1$ $1\oplus1\oplus0=1$ $1\oplus1\oplus1=1$ $1\oplus1=0$
answered
May 28
in
Digital Logic
by
asthajain10101

230
views
nielit2016marscientistb
0
votes
1
answer
5
NIELIT 2016 DEC Scientist B (IT)  Section B: 35
What will be the final output of D flipFlop if the input string is $0010011100$? $1$ $0$ Don’t Care None of the above
answered
May 28
in
Digital Logic
by
Mohit Kumar 6
Active

63
views
nielit2016decscientistbit
+5
votes
4
answers
6
The number of possible boolean functions that can be defined for n boolean variables over n valued boolean algebra is
answered
May 27
in
Digital Logic
by
harypotter0

1.5k
views
digitallogic
booleanalgebra
+59
votes
8
answers
7
GATE2015248
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 ... carry binary adder is implemented by using four full adders. The total propagation time of this 4bit binary adder in microseconds is ______.
answered
May 26
in
Digital Logic
by
Gaurav Yadav
Junior

16.5k
views
gate20152
digitallogic
adder
normal
numericalanswers
+60
votes
5
answers
8
GATE200640
Consider numbers represented in 4bit Gray code. Let $ h_{3}h_{2}h_{1}h_{0}$ be the Gray code representation of a number $n$ and let $ g_{3}g_{2}g_{1}g_{0}$ be the Gray code of $ (n+1)(modulo 16)$ ... $ g_{3}(h_{3}h_{2}h_{1}h_{0})=\sum (0,1,6,7,10,11,12,13) $
answered
May 26
in
Digital Logic
by
Gaurav Yadav
Junior

7.2k
views
gate2006
digitallogic
numberrepresentation
binarycodes
normal
0
votes
1
answer
9
NIELIT 2016 MAR Scientist B  Section C: 4
In a ripple counter using edge triggered $JK$ flipflops, the pulse input is applied to the clock input of all flipflops clock input of one flipflop $J$ and $K$ inputs of all flipflops $J$ and $K$ inputs of one flip flop
answered
May 26
in
Digital Logic
by
Mohit Kumar 6
Active

91
views
nielit2016marscientistb
+1
vote
2
answers
10
UGCNETDec2013II: 6
FAN IN of a component A is defined as Number of components that can call or pass control to component A Number of components that are called by component A Number of components related to component A Number of components dependent on component A
answered
May 25
in
Digital Logic
by
IITB2020

1.3k
views
ugcnetdec2013ii
digitallogic
+7
votes
3
answers
11
ISRO201421, UGCNETDec2012III: 23, UGCNETDec2013III: 22
What are the final values of $Q_1$ and $Q_0$ after 4 clock cycles, if initial values are 00 in the sequential circuit shown below: 11 01 10 00
answered
May 25
in
Digital Logic
by
IITB2020

5.6k
views
isro2014
digitallogic
circuitoutput
ugcnetdec2012iii
ugcnetdec2013iii
+1
vote
2
answers
12
UGCNETAUG2016II: 7
Which of the following is the most efficient to perform arithmetic operations on the numbers ? Signmagnitude $1's$ complement $2's$ complement $9's$ complement
answered
May 25
in
Digital Logic
by
IITB2020

699
views
ugcnetaug2016ii
digitallogic
numberrepresentation
0
votes
2
answers
13
UGCNETAUG2016II: 6
The octal number $326.4$ is equivalent to $(214.2)_{10}$ and $(D6.8)_{16}$ $(212.5)_{10}$ and $(D6.8)_{16}$ $(214.5)_{10}$ and $(D6.8)_{16}$ $(214.5)_{10}$ and $(D6.4)_{16}$
answered
May 25
in
Digital Logic
by
IITB2020

1.1k
views
ugcnetaug2016ii
digitallogic
numberrepresentation
+7
votes
5
answers
14
ISRO201510
The boolean expression $AB+AB'+A'C+AC$ is independent of the boolean variable A B C None of these
answered
May 25
in
Digital Logic
by
IITB2020

3k
views
isro2015
digitallogic
booleanalgebra
+18
votes
6
answers
15
GATE2016130
Consider the two cascade $2$ to $1$ multiplexers as shown in the figure . The minimal sum of products form of the output $X$ is $\overline{P} \ \overline {Q}+PQR$ $\overline{P} \ {Q}+QR$ $PQ +\overline{P} \ \overline{Q}R$ $\overline{Q} \ \overline{R} + PQR$
answered
May 25
in
Digital Logic
by
IITB2020

3.5k
views
gate20161
digitallogic
multiplexer
normal
+21
votes
2
answers
16
GATE2005IT11
How many pulses are needed to change the contents of a $8$bit up counter from $10101100$ to $00100111$ (rightmost bit is the LSB)? $134$ $133$ $124$ $123$
answered
May 25
in
Digital Logic
by
IITB2020

2.5k
views
gate2005it
digitallogic
digitalcounter
normal
+27
votes
5
answers
17
GATE2005IT7
Which of the following expressions is equivalent to $(A \oplus B) \oplus C$ $(A + B + C) (\bar A +\bar B +\bar C)$ $(A + B + C) (\bar A +\bar B + C)$ $ABC + \bar A (B \oplus C) + \bar B(A \oplus C)$ None of these
answered
May 25
in
Digital Logic
by
IITB2020

2.5k
views
gate2005it
digitallogic
normal
booleanalgebra
+33
votes
6
answers
18
GATE2015137
A positive edgetriggered $D$ flipflop is connected to a positive edgetriggered $JK$ flipflop as follows. The $Q$ output of the $D$ flipflop is connected to both the $J$ and $K$ inputs of the $JK$ flipflop, while the $Q$ output of ... of the $JK$ flipflops. Both the flipflops have nonzero propagation delays. $0110110\ldots$ $0100100\ldots$ $011101110\ldots$ $011001100\ldots$
answered
May 25
in
Digital Logic
by
Gaurav Yadav
Junior

5.1k
views
gate20151
digitallogic
flipflop
normal
+77
votes
14
answers
19
GATE201618
We want to design a synchronous counter that counts the sequence $010203$ and then repeats. The minimum number of $\text{JK}$ flipflops required to implement this counter is _____________.
answered
May 22
in
Digital Logic
by
iwasifirshad

19.9k
views
gate20161
digitallogic
digitalcounter
flipflop
normal
numericalanswers
+41
votes
3
answers
20
GATE200221
Consider the following logic circuit whose inputs are functions $f_1, f_2, f_3$ and output is $f$ Given that $f_1(x,y,z) = \Sigma (0,1,3,5)$ $f_2(x,y,z) = \Sigma (6,7),$ and $f(x,y,z) = \Sigma (1,4,5).$ $f_3$ is $\Sigma (1,4,5)$ $\Sigma (6,7)$ $\Sigma (0,1,3,5)$ None of the above
answered
May 22
in
Digital Logic
by
Gaurav Yadav
Junior

4.6k
views
gate2002
digitallogic
normal
canonicalnormalform
circuitoutput
+29
votes
3
answers
21
GATE19992.16
The number of full and halfadders required to add $16$bit numbers is $8$ halfadders, $8$ fulladders $1$ halfadder, $15$ fulladders $16$ halfadders, $0$ fulladders $4$ halfadders, $12$ fulladders
answered
May 21
in
Digital Logic
by
Gaurav Yadav
Junior

6.6k
views
gate1999
digitallogic
normal
adder
0
votes
1
answer
22
Made Easy Test Series, Digital logic
Q) The sum of product (SOP) form of logic expression is most suitable for designing logic circuit using only A.) AND gates B.) NAND gates C.) EXOR gates D.) NOR gates
answered
May 20
in
Digital Logic
by
Mohit Kumar 6
Active

136
views
madeeasytestseries
digitallogic
0
votes
1
answer
23
sequential circuit
What is output Y?
answered
May 19
in
Digital Logic
by
srestha
Veteran

62
views
0
votes
1
answer
24
Synchronous Counter
answered
May 19
in
Digital Logic
by
srestha
Veteran

218
views
digitallogic
synchronousasynchronouscircuits
digitalcounter
0
votes
1
answer
25
Digital Logic Morris Mono 5.6
A sequential circuit with two $D$ flipflops $A$ and $B$, two inputs $x$ and $y$, and one output $z$ is specified by the following nextstate and output equations : $A(t+1)= x'y + xB$ $B(t+1)= x'A + xB$ $z = A$ (a) Draw the logic diagram of the circuit. (b) List the state table for the sequential circuit. (c) Draw the corresponding state diagram.
answered
May 16
in
Digital Logic
by
srestha
Veteran

356
views
digitallogic
sequential
referencebook
+1
vote
3
answers
26
UGCNETDec2013II: 32
Given that $(292)_{10} = (1204)_x$ in some number system $x$. The base $x$ of that number system is 2 8 10 None of the above
answered
May 16
in
Digital Logic
by
Girjesh Chouhan

2k
views
ugcnetdec2013ii
digitallogic
numbersystem
0
votes
2
answers
27
Question on Kmaps
Given explanation. I am not able to understand what is asked in the question. Please explain.
answered
May 14
in
Digital Logic
by
srestha
Veteran

3.4k
views
digitallogic
kmap
0
votes
2
answers
28
Number of Gate levels required
answered
May 14
in
Digital Logic
by
srestha
Veteran

312
views
digitallogic
testseries
+2
votes
2
answers
29
MadeEasy Test Series: Digital Logic  Carry Generator
The number of AND gates are present inside a 5bit carry look ahead generator circuit are ______.
answered
May 14
in
Digital Logic
by
srestha
Veteran

332
views
digitallogic
carrygenerator
madeeasytestseries
0
votes
1
answer
30
Please explain how to approach such problems
Given explanation: I always fail to solve such questions. Please tell what is the approach to solve such problems?
answered
May 14
in
Digital Logic
by
srestha
Veteran

142
views
digitallogic
0
votes
1
answer
31
Morris Mano Edition 3 Exercise 7 Question 39 (Page No. 305)
Given that 11bit data word 11001001010, generate the 15bit hamming code word.
answered
May 13
in
Digital Logic
by
Divyanshu nauni

39
views
digitallogic
morrismano
hammingcode
+1
vote
2
answers
32
ISRO202052
To send same bit sequence, NRZ encoding require Same clock frequency as Manchester encoding Half the clock frequency as Manchester encoding Twice the clock frequency as Manchester encoding A clock frequency which depend on number of zeroes and ones in the bit sequence
answered
May 7
in
Digital Logic
by
DIBAKAR MAJEE
Active

308
views
isro2020
digitallogic
normal
0
votes
2
answers
33
NIELIT 2016 DEC Scientist B (IT)  Section B: 45
Which will be the equation of simplification of the given Kmap? $AB' + B'CD' + A'B'C'$ $AB' + A'B'D' + A'B'C'$ $B'D' + AB' + B'C'$ $B'D' + A'B'C' + AB'$
answered
May 6
in
Digital Logic
by
abhishek tiwary
Active

75
views
nielit2016decscientistbit
0
votes
2
answers
34
NIELIT 2016 DEC Scientist B (CS)  Section B: 33
What will be the Excess$3$ code for $1001$? $1001$ $1010$ $1011$ $1100$
answered
May 4
in
Digital Logic
by
abhishek tiwary
Active

71
views
nielit2016decscientistbcs
0
votes
1
answer
35
NIELIT 2016 DEC Scientist B (IT)  Section B: 53
What is $2$'s complement of $(101)_3$? $(010)_3$ $(011)_3$ $(121)_3$ $(121)_2$
answered
May 4
in
Digital Logic
by
abhishek tiwary
Active

70
views
nielit2016decscientistbit
0
votes
1
answer
36
Digital Design by Morris Mano
4.11 Using four halfadders (HDLsee Problem 4.52), (a) Design a fullsubtractor circuit incrementer. (A circuit that adds one to a fourbit binary number.) (b) Design a fourbit combinational decrementer (a circuit that subtracts 1 from ... form, so is it possible to design the circuit using only four half adders if we assume the number is in Unsigned Representation?
answered
May 4
in
Digital Logic
by
shubham02

217
views
+3
votes
4
answers
37
ISI2017DCG10
The value of the Boolean expression (with usual definitions) $(A’BC’)’ +(AB’C)’$ is $0$ $1$ $A$ $BC$
answered
May 3
in
Digital Logic
by
DIBAKAR MAJEE
Active

241
views
isi2017dcg
digitallogic
booleanalgebra
booleanexpression
+8
votes
6
answers
38
ISRO20157
If half adders and full adders are implements using gates, then for the addition of two 17 bit numbers (using minimum gates) the number of half adders and full adders required will be 0,17 16,1 1,16 8,8
answered
May 3
in
Digital Logic
by
Pradosh123

5.6k
views
isro2015
digitallogic
adder
+2
votes
4
answers
39
UGCNETDec2014II: 06
The $BCD$ adder to add two decimal digits needs minimum of $6$ full adders and $2$ half adders $5$ full adders and $3$ half adders $4$ full adders and $3$ half adders $5$ full adders and $2$ half adders
answered
Apr 30
in
Digital Logic
by
Girjesh Chouhan

1k
views
ugcnetdec2014ii
digitallogic
adders
+1
vote
4
answers
40
the mimimum no of 2input nand gates required to implement th function F=(x'+y')(z+w)?
answered
Apr 27
in
Digital Logic
by
DIBAKAR MAJEE
Active

5.7k
views
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