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Recent questions tagged circuit-output
6
votes
3
answers
1
ISRO2020-66
The following circuit compares two $2$-bit binary numbers, $X$ and $Y$ represented by $X_1X_0$ and $Y_1Y_0$ respectively. ($X_0$ and $Y_0$ represent Least Significant Bits) Under what conditions $Z$ will be $1$? $X>Y$ $X<Y$ $X=Y$ $X!=Y$
Satbir
asked
in
Digital Logic
Jan 13, 2020
by
Satbir
2.2k
views
isro-2020
digital-logic
digital-circuits
circuit-output
normal
6
votes
3
answers
2
ISRO2020-12
If $ABCD$ is a $4$-bit binary number, then what is the code generated by the following circuit? BCD code Gray code $8421$ code Excess-$3$ code
Satbir
asked
in
Digital Logic
Jan 13, 2020
by
Satbir
1.9k
views
isro-2020
digital-logic
combinational-circuit
circuit-output
normal
4
votes
2
answers
3
ISRO2020-11
Minimum number of NAND gates required to implement the following binary equation $Y = (\overline{A}+\overline{B})(C+D)$ $4$ $5$ $3$ $6$
Satbir
asked
in
Digital Logic
Jan 13, 2020
by
Satbir
3.0k
views
isro-2020
digital-logic
combinational-circuit
circuit-output
normal
3
votes
3
answers
4
ISRO2020-77
Consider the following circuit The function by the network above is $\overline{AB}E+EF+\overline{CD}F$ $(\overline{E}+AB\overline{F})(C+D+\overline{F})$ $(\overline{AB}+E)(\overline{E}+\overline{F})(C+D+\overline{F})$ $(A+B)\overline{E} +\overline{EF}+CD\overline{F}$
Satbir
asked
in
Digital Logic
Jan 13, 2020
by
Satbir
1.7k
views
isro-2020
digital-logic
combinational-circuit
circuit-output
normal
0
votes
1
answer
5
Morris Mano Edition 3 Exercise 6 Question 15,16 (Page No. 254)
Starting from a state of the state table given below find out the output sequence generated with an input sequence 01110010011. reduce the same table and repeat the same sequence with the given input sequence. Show that same output is obtained.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
1.4k
views
digital-logic
sequential-circuit
synchronous-asynchronous-circuits
circuit-output
2
votes
1
answer
6
Morris Mano Edition 3 Exercise 6 Question 14 (Page No. 254)
Reduce the number of states in the following state table and tabulate the reduced state table.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
4.0k
views
digital-logic
sequential-circuit
synchronous-asynchronous-circuits
circuit-output
1
vote
0
answers
7
Morris Mano Edition 3 Exercise 6 Question 13 (Page No. 254)
Starting from state 00 in the state transition diagram of the figure. Determine the state transitions and output sequence that will be generated when the input sequence of 010110111011110 is applied.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
1.7k
views
digital-logic
sequential-circuit
circuit-output
synchronous-asynchronous-circuits
1
vote
0
answers
8
Morris Mano Edition 3 Exercise 4 Question 24 (Page No. 151)
Derive the truth table for the output of each NOR gate in the given figure.
ajaysoni1924
asked
in
Digital Logic
Apr 2, 2019
by
ajaysoni1924
235
views
digital-logic
morris-mano
combinational-circuit
circuit-output
1
vote
2
answers
9
Morris Mano Edition 3 Exercise 4 Question 22 (Page No. 151)
Verify the Circuit generates the Exclusive NOR Functions.
ajaysoni1924
asked
in
Digital Logic
Apr 2, 2019
by
ajaysoni1924
529
views
digital-logic
morris-mano
combinational-circuit
circuit-output
1
vote
1
answer
10
Morris Mano Edition 3 Exercise 4 Question 21 (Page No. 151)
Determine the boolean function for the outputs F and G as a function of Four inputs A, B, C, And D.
ajaysoni1924
asked
in
Digital Logic
Apr 2, 2019
by
ajaysoni1924
692
views
digital-logic
morris-mano
combinational-circuit
circuit-output
0
votes
1
answer
11
MadeEasy Subject Test 2019: Digital Logic - Circuit Output
Assume the operands are in 2’s Complement. To decrement A by 1, lines K,Cn and B should be : K = 1 , Cin = 1 , B = 1 K = 0 , Cin = 1 , B = 1 K = 0 , Cin = 1 , B = 0 K = 1 , Cin = 0 , B = 0
Na462
asked
in
Digital Logic
Jan 16, 2019
by
Na462
1.1k
views
digital-logic
circuit-output
made-easy-test-series
3
votes
0
answers
12
MadeEasy Full Length Test 2018: Digital Logic - Circuit Output
Consider the below Digital Circuit : The State Transition diagram on circuit is :
Na462
asked
in
Digital Logic
Jan 13, 2019
by
Na462
554
views
digital-logic
circuit-output
made-easy-test-series
0
votes
1
answer
13
MadeEasy Workbook: Digital Logic - Circuit Output
How the table is generated?
Jyoti Kumari97
asked
in
Digital Logic
Dec 30, 2018
by
Jyoti Kumari97
361
views
made-easy-booklet
digital-logic
circuit-output
0
votes
2
answers
14
GATE Overflow | Mock GATE | Test 1 | Question: 59
Assume the initial values of $K0$, $Q_0$ and $Q_1$ to be $1$. Which of the following state transition tables correctly correspond to the circuit given above? (Note: $Q_{kN}$ and $Q_{kN+1}$ ...
Ruturaj Mohanty
asked
in
Digital Logic
Dec 27, 2018
by
Ruturaj Mohanty
575
views
go-mockgate-1
digital-circuits
circuit-output
digital-logic
1
vote
2
answers
15
Gateforum Test Series: Digital Logic - Circuit Output
Answer is provided as C. But D should be the answer. Please confirm
Gupta731
asked
in
Digital Logic
Nov 7, 2018
by
Gupta731
457
views
digital-logic
gateforum-test-series
circuit-output
1
vote
1
answer
16
Gateforum Test Series: Digital Logic - Circuit Output
I think all options are wrong.
Gupta731
asked
in
Digital Logic
Nov 7, 2018
by
Gupta731
479
views
gateforum-test-series
digital-logic
circuit-output
0
votes
2
answers
17
MadeEasy Workbook: Digital Logic - Circuit Output
What should be the answer...
anonymous
asked
in
Digital Logic
Sep 26, 2018
by
anonymous
282
views
digital-logic
circuit-output
made-easy-booklet
13
votes
3
answers
18
ISRO2018-9
In the diagram above, the inverter (NOT gate) and the AND-gates labeled $1$ and $2$ have delays of $9, 10$ and $12$ nanoseconds (ns), respectively. Wire delays are negligible. For certain values $a$ and $c$, together with certain transition of $b$, a glitch (spurious output) is ... correct value. The duration of glitch is: $7\;\text{ns}$ $9\;\text{ns}$ $11\;\text{ns}$ $13\;\text{ns}$
Arjun
asked
in
Digital Logic
Apr 22, 2018
by
Arjun
4.5k
views
isro2018
digital-logic
circuit-output
5
votes
1
answer
19
GATE CSE 1996 | Question: 24-b
Consider the synchronous sequential circuit in the below figure Given that the initial state of the circuit is $S_4,$ identify the set of states, which are not reachable.
go_editor
asked
in
Digital Logic
Feb 10, 2018
by
go_editor
1.8k
views
gate1996
normal
digital-logic
circuit-output
descriptive
1
vote
0
answers
20
MadeEasy Full Length Test 2018: Digital Logic - Circuit Output
Abhishek Kumar Singh
asked
in
Digital Logic
Jan 18, 2018
by
Abhishek Kumar Singh
419
views
digital-logic
circuit-output
made-easy-test-series
1
vote
1
answer
21
MadeEasy Subject Test: Digital Logic - Circuit Output
charul
asked
in
Digital Logic
Nov 27, 2017
by
charul
395
views
made-easy-test-series
digital-logic
circuit-output
sequential-circuit
4
votes
2
answers
22
Virtual Gate Test Series: Digital Logic - Flip Flops
Manoja Rajalakshmi A
asked
in
Digital Logic
Nov 13, 2017
by
Manoja Rajalakshmi A
955
views
digital-logic
sequential-circuit
flip-flop
circuit-output
virtual-gate-test-series
0
votes
2
answers
23
Test by Bikram | Mock GATE | Test 4 | Question: 29
The value of $ f + g $ in the above circuit is: $x{}'y + x{}'z + yz + yz{}'$ $x{}'y + x{}'z + y{}'z'+ y{}'z$ $x{}'y + y{}'z{}' + yz + x{}'z$ $xy + y{}'z{}'+ x{}'z + yz$
Bikram
asked
in
Digital Logic
May 14, 2017
by
Bikram
238
views
tbb-mockgate-4
digital-logic
multiplexer
circuit-output
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