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Recent questions tagged circuitoutput
+1
vote
1
answer
1
GATE199624b
Consider the synchronous sequential circuit in the below figure Given that the initial state of the circuit is S$_4$, identify the set of states, which are not reachable.
asked
Feb 10
in
Digital Logic
by
jothee
Veteran
(
98.8k
points)

99
views
gate1996
normal
digitallogic
circuitoutput
+4
votes
1
answer
2
virtual gate
asked
Nov 13, 2017
in
Digital Logic
by
Manoja Rajalakshmi A
Active
(
2.5k
points)

108
views
flipflop
virtualgate
circuitoutput
+9
votes
1
answer
3
GATE19882v
Three switching functions $f_1, \: f_2 \:$ and $f_3$ are expressed below as sum of minterms. $f_1 (w, x, y, z) = \sum \: 0, 1, 2, 3, 5, 12$ $f_2 (w, x, y, z) = \sum \: 0, 1, 2, 10, 13, 14, 15$ $f_3 (w, x, y, z) = \sum \: 2, 4, 5, 8$ Express the function $f$ realised by the circuit shown in the below figure as the sum of minterms (in decimal notation).
asked
Dec 11, 2016
in
Digital Logic
by
jothee
Veteran
(
98.8k
points)

384
views
gate1988
descriptive
digitallogic
easy
circuitoutput
minsumofproductsform
+3
votes
3
answers
4
GATE19894ix
Provide short answers to the following questions: Explain the behaviour of the following logic circuit (Fig.4) with level input A and output B
asked
Nov 30, 2016
in
Digital Logic
by
makhdoom ghaya
Boss
(
39.7k
points)

413
views
gate1989
descriptive
digitallogic
circuitoutput
0
votes
2
answers
5
Simple Doubt in digital
Consider a simple OR gate with 2 inputs A and B, a ouput O which is taken back and reconnected to B as feedback. Now, A=0 and B=0 so O=0. If we give A=1 for like 1 sec , O=1 and now if we turn off the power from the circuit , 1.) will we get a infinite ... it and and O=1 (Assume a case when A=1,B=0 so O=1 , Now i quickly set A=0 , will this not automatically make B=1) ?
asked
Nov 27, 2016
in
Digital Logic
by
Aakash Das
Junior
(
551
points)

236
views
digitallogic
combinational
digitalcircuits
circuitoutput
logicgates
+2
votes
3
answers
6
GATE19903i
Choose the correct alternatives (More than one may be correct). Two NAND gates having open collector outputs are tied together as shown in below figure. The logic function Y, implemented by the circuit is, $Y=ABC + DE$ $Y=ABC + DE$ $Y=ABC.DE$ $Y=ABC.DE$
asked
Nov 19, 2016
in
Digital Logic
by
makhdoom ghaya
Boss
(
39.7k
points)

583
views
gate1990
normal
digitallogic
circuitoutput
+10
votes
2
answers
7
GATE198713a
The below figure shows four Dtype flipflops connnected as a shift register using an $XOR$ gate. The initial state and three subsequent states for three clock pulses are also given. State $Q_{A}$ $Q_{B}$ $Q_{C}$ $Q_{D}$ Initial 1 1 1 1 After the first clock 0 1 1 ... third clock 0 0 0 1 The state $Q_{A} Q_{B} Q_{C} Q_{D}$ after the fourth clock pulse is $0000$ $1111$ $1001$ $1000$
asked
Nov 15, 2016
in
Digital Logic
by
makhdoom ghaya
Boss
(
39.7k
points)

490
views
gate1987
digitallogic
circuitoutput
shiftregisters
+6
votes
1
answer
8
GATE19871IV
The output $F$ of the below multiplexer circuit can be represented by $AB+B\bar{C}+\bar{C}A+\bar{B}\bar{C}$ $A\oplus B\oplus C$ $A \oplus B$ $\bar{A} \bar{B} C+ \bar{A} B \bar{C}+A \bar{B} \bar{C}$
asked
Nov 8, 2016
in
Digital Logic
by
makhdoom ghaya
Boss
(
39.7k
points)

430
views
gate1987
digitallogic
circuitoutput
multiplexer
0
votes
2
answers
9
UGCNETDec2012II1
Consider the circuit shown below. IN a certain steady state, ‘Y’ is at logical ‘l’. What are the possible values of A, B, C? A=0, B=0, C=1 A=0, B=C=1 A=1, B=C=0 A= B=1, C=1
asked
Jul 8, 2016
in
Digital Logic
by
jothee
Veteran
(
98.8k
points)

834
views
ugcnetdec2012ii
digitallogic
circuitoutput
+6
votes
1
answer
10
ISRO201613
The circuit given in the figure below is An oscillating circuit and its output is square wave The one whose output remains stable in '1' state The one having output remains stable in '0' state has a single pulse of three times propagation delay
asked
Jul 5, 2016
in
Digital Logic
by
jothee
Veteran
(
98.8k
points)

2.3k
views
isro2016
digitallogic
circuitoutput
+6
votes
2
answers
11
ISRO201610
Consider the following gate network Which one of the following gates is redundant? Gate No. 1 Gate No. 2 Gate No. 3 Gate No. 4
asked
Jul 5, 2016
in
Digital Logic
by
jothee
Veteran
(
98.8k
points)

3.6k
views
isro2016
digitallogic
circuitoutput
+6
votes
3
answers
12
ISRO201453
Consider the logic circuit given below. The inverter, AND and OR gates have delays of 6, 10 and 11 nanoseconds respectively. Assuming that wire delays are negligible, what is the duration of glitch for Q before it becomes stable? 5 11 16 27
asked
Jul 1, 2016
in
Digital Logic
by
jothee
Veteran
(
98.8k
points)

2.4k
views
isro2014
digitallogic
circuitoutput
+3
votes
4
answers
13
ISRO201415
Consider the logic circuit given below: Q=__________? $\bar{A} C + B \bar{C} +CD$ $ABC + \bar{C} D$ $AB + B \bar{C} + B \bar{D}$ $A \bar{B} + A \bar{C} + \bar{C} D$
asked
Jul 1, 2016
in
Digital Logic
by
jothee
Veteran
(
98.8k
points)

1.9k
views
isro2014
digitallogic
circuitoutput
+5
votes
1
answer
14
ISRO200827
The output Y of the given circuit 1 0 X X'
asked
Jun 12, 2016
in
Digital Logic
by
jothee
Veteran
(
98.8k
points)

1.4k
views
isro2008
digitallogic
circuitoutput
+6
votes
1
answer
15
ISRO200826
The logic operations of two combinational circuits in FigureI and Figure II are entirely different identical complementary dual
asked
Jun 12, 2016
in
Digital Logic
by
jothee
Veteran
(
98.8k
points)

1.4k
views
isro2008
digitallogic
circuitoutput
+4
votes
2
answers
16
ISRO200812
In the given network of AND and OR gates $f$ can be written as $X_0X_1X_2 \dots X_n + X_1X_2 \dots X_n + X_2X_3 \dots X_n + \dots + X_n$ $X_0X_1 + X_2X_3+ \dots X_{n1}X_n$ $X_0+X_1 + X_2+ \dots +X_n $ $X_0X_1 + X_3 \dots X_{n1}+ X_2X_3 + X_5 \dots X_{n1} + \dots +X_{n2} X_{n1} +X_n$
asked
Jun 11, 2016
in
Digital Logic
by
jothee
Veteran
(
98.8k
points)

1.6k
views
isro2008
digitallogic
circuitoutput
+13
votes
1
answer
17
GATE201151
Consider the following circuit involving three Dtype flipflops used in a certain type of counter configuration. If all the flipflops were reset to 0 at power on, what is the total number of distinct outputs (states) represented by $PQR$ generated by the counter? 3 4 5 6
asked
Apr 21, 2016
in
Digital Logic
by
jothee
Veteran
(
98.8k
points)

1.1k
views
gate2011
digitallogic
circuitoutput
normal
+16
votes
9
answers
18
GATE199363
Multiple choices can be correct. Mark all of them. For the initial state of 000, the function performed by the arrangement of the JK flipflops in figure is: Shift Register Mod 3 Counter Mod 6 Counter Mod 2 Counter None of the above
asked
Sep 20, 2015
in
Digital Logic
by
jothee
Veteran
(
98.8k
points)

1.9k
views
gate1993
digitallogic
circuitoutput
normal
+5
votes
1
answer
19
GATE1993_6.2
If the state machine described in figure, should have a stable state, the restriction on the inputs given by $a.b=1$ $a+b=1$ $\bar{a} + \bar{b} =0$ $\overline{a.b}=1$ $\overline{a+b} =1$
asked
Sep 20, 2015
in
Digital Logic
by
jothee
Veteran
(
98.8k
points)

775
views
gate1993
digitallogic
normal
circuitoutput
+1
vote
2
answers
20
what is 9 clock cycles what are output at q0 q1 q2?
asked
Sep 4, 2015
in
Digital Logic
by
Ravi Raaja
(
195
points)

309
views
digitallogic
sequential
circuitoutput
+5
votes
2
answers
21
ISRO201421, UGCNETDec2012III23, UGCNETDec2013III22
asked
Jul 17, 2015
in
Digital Logic
by
focus _GATE
Boss
(
20.4k
points)

3.3k
views
isro2014
digitallogic
circuitoutput
ugcnetdec2012iii
ugcnetdec2013iii
+15
votes
4
answers
22
GATE2005IT43
Which of the following input sequences will always generate a 1 at the output z at the end of the third cycle? A B C 0 0 0 1 0 1 1 1 1 A B C 1 0 1 1 1 0 1 1 1 A B C 0 1 1 1 0 1 1 1 1 A B C 0 0 1 1 1 0 1 1 1
asked
Nov 4, 2014
in
Digital Logic
by
Ishrat Jahan
Boss
(
19.1k
points)

3.1k
views
gate2005it
digitallogic
circuitoutput
normal
+13
votes
1
answer
23
GATE2005IT10
A twoway switch has three terminals a, b and c. In ON position (logic value 1), a is connected to b, and in OFF position, a is connected to c. Two of these twoway switches S1 and S2 are connected to a bulb as shown below. Which of the following ... true, will always result in the lighting of the bulb ? $S1.\overline{S2}$ $S1 + S2$ $\overline {S1\oplus S2}$ $S1 \oplus S2$
asked
Nov 3, 2014
in
Digital Logic
by
Ishrat Jahan
Boss
(
19.1k
points)

1k
views
gate2005it
digitallogic
circuitoutput
normal
+16
votes
2
answers
24
GATE2006IT36
The majority function is a Boolean function $f(x, y, z)$ that takes the value 1 whenever a majority of the variables $x,y,z$ are 1. In the circuit diagram for the majority function shown below, the logic gates for the boxes labeled P and Q are, respectively, XOR, AND XOR, XOR OR, OR OR, AND
asked
Oct 31, 2014
in
Digital Logic
by
Ishrat Jahan
Boss
(
19.1k
points)

1.7k
views
gate2006it
digitallogic
circuitoutput
normal
+15
votes
6
answers
25
GATE2007IT45
The line T in the following figure is permanently connected to the ground. Which of the following inputs (X1 X2 X3 X4) will detect the fault ? 0000 0111 1111 None of these
asked
Oct 30, 2014
in
Digital Logic
by
Ishrat Jahan
Boss
(
19.1k
points)

1.8k
views
gate2007it
digitallogic
circuitoutput
normal
+12
votes
5
answers
26
GATE2007IT40
What is the final value stored in the linear feedback shift register if the input is 101101? 0110 1011 1101 1111
asked
Oct 30, 2014
in
Digital Logic
by
Ishrat Jahan
Boss
(
19.1k
points)

1k
views
gate2007it
digitallogic
circuitoutput
normal
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