Recent questions tagged circuit-output

+1 vote

1 answer

1

GATE1996-24-b
Consider the synchronous sequential circuit in the below figure Given that the initial state of the circuit is S$_4$, identify the set of states, which are not reachable.

asked Feb 10 in Digital Logic by jothee Veteran (99.8k points) | 187 views

+4 votes

2 answers

2

virtual gate

asked Nov 13, 2017 in Digital Logic by Manoja Rajalakshmi A Active (3.2k points) | 164 views

+10 votes

1 answer

3

GATE1988-2-v
Three switching functions $f_1, \: f_2 \:$ and $f_3$ are expressed below as sum of minterms. $f_1 (w, x, y, z) = \sum \: 0, 1, 2, 3, 5, 12$ $f_2 (w, x, y, z) = \sum \: 0, 1, 2, 10, 13, 14, 15$ $f_3 (w, x, y, z) = \sum \: 2, 4, 5, 8$ Express the function $f$ realised by the circuit shown in the below figure as the sum of minterms (in decimal notation).

asked Dec 11, 2016 in Digital Logic by jothee Veteran (99.8k points) | 510 views

+3 votes

3 answers

4

GATE1989-4-ix
Provide short answers to the following questions: Explain the behaviour of the following logic circuit (Fig.4) with level input A and output B

asked Nov 30, 2016 in Digital Logic by makhdoom ghaya Boss (40.1k points) | 462 views

0 votes

2 answers

5

Simple Doubt in digital
Consider a simple OR gate with 2 inputs A and B, a ouput O which is taken back and reconnected to B as feedback. Now, A=0 and B=0 so O=0. If we give A=1 for like 1 sec , O=1 and now if we turn off the power from the circuit , 1.) will we get a infinite ... it and and O=1 (Assume a case when A=1,B=0 so O=1 , Now i quickly set A=0 , will this not automatically make B=1) ?

asked Nov 27, 2016 in Digital Logic by Aakash Das Junior (551 points) | 272 views

+2 votes

3 answers

6

GATE1990-3-i
Choose the correct alternatives (More than one may be correct). Two NAND gates having open collector outputs are tied together as shown in below figure. The logic function Y, implemented by the circuit is, $Y=ABC + DE$ $Y=ABC + DE$ $Y=ABC.DE$ $Y=ABC.DE$

asked Nov 19, 2016 in Digital Logic by makhdoom ghaya Boss (40.1k points) | 687 views

+11 votes

2 answers

7

GATE1987-13-a
The below figure shows four D-type flip-flops connected as a shift register using a $XOR$ gate. The initial state and three subsequent states for three clock pulses are also given. State $Q_{A}$ $Q_{B}$ $Q_{C}$ $Q_{D}$ Initial $1$ $1$ $1$ $1$ After the first clock ... clock $0$ $0$ $0$ $1$ The state $Q_{A} Q_{B} Q_{C} Q_{D}$ after the fourth clock pulse is $0000$ $1111$ $1001$ $1000$

asked Nov 15, 2016 in Digital Logic by makhdoom ghaya Boss (40.1k points) | 602 views

+7 votes

1 answer

8

GATE1987-1-IV
The output $F$ of the below multiplexer circuit can be represented by $AB+B\bar{C}+\bar{C}A+\bar{B}\bar{C}$ $A\oplus B\oplus C$ $A \oplus B$ $\bar{A} \bar{B} C+ \bar{A} B \bar{C}+A \bar{B} \bar{C}$

asked Nov 8, 2016 in Digital Logic by makhdoom ghaya Boss (40.1k points) | 507 views

0 votes

2 answers

9

UGCNET-Dec2012-II-1
Consider the circuit shown below. IN a certain steady state, ‘Y’ is at logical ‘l’. What are the possible values of A, B, C? A=0, B=0, C=1 A=0, B=C=1 A=1, B=C=0 A= B=1, C=1

asked Jul 8, 2016 in Digital Logic by jothee Veteran (99.8k points) | 1.1k views

+6 votes

1 answer

10

ISRO2016-13
The circuit given in the figure below is An oscillating circuit and its output is square wave The one whose output remains stable in '1' state The one having output remains stable in '0' state has a single pulse of three times propagation delay

asked Jul 5, 2016 in Digital Logic by jothee Veteran (99.8k points) | 2.5k views

+6 votes

2 answers

11

ISRO2016-10
Consider the following gate network Which one of the following gates is redundant? Gate No. 1 Gate No. 2 Gate No. 3 Gate No. 4

asked Jul 5, 2016 in Digital Logic by jothee Veteran (99.8k points) | 3.8k views

+5 votes

3 answers

12

ISRO2014-53
Consider the logic circuit given below. The inverter, AND and OR gates have delays of 6, 10 and 11 nanoseconds respectively. Assuming that wire delays are negligible, what is the duration of glitch for Q before it becomes stable? 5 11 16 27

asked Jul 1, 2016 in Digital Logic by jothee Veteran (99.8k points) | 2.7k views

+3 votes

4 answers

13

ISRO2014-15
Consider the logic circuit given below: Q=__________? $\bar{A} C + B \bar{C} +CD$ $ABC + \bar{C} D$ $AB + B \bar{C} + B \bar{D}$ $A \bar{B} + A \bar{C} + \bar{C} D$

asked Jul 1, 2016 in Digital Logic by jothee Veteran (99.8k points) | 2k views

+4 votes

1 answer

14

ISRO2008-27
The output Y of the given circuit 1 0 X X'

asked Jun 12, 2016 in Digital Logic by jothee Veteran (99.8k points) | 1.5k views

+5 votes

1 answer

15

ISRO2008-26
The logic operations of two combinational circuits in Figure-I and Figure -II are entirely different identical complementary dual

asked Jun 12, 2016 in Digital Logic by jothee Veteran (99.8k points) | 1.5k views

+3 votes

2 answers

16

ISRO2008-12
In the given network of AND and OR gates $f$ can be written as $X_0X_1X_2 \dots X_n + X_1X_2 \dots X_n + X_2X_3 \dots X_n + \dots + X_n$ $X_0X_1 + X_2X_3+ \dots X_{n-1}X_n$ $X_0+X_1 + X_2+ \dots +X_n $ $X_0X_1 + X_3 \dots X_{n-1}+ X_2X_3 + X_5 \dots X_{n-1} + \dots +X_{n-2} X_{n-1} +X_n$

asked Jun 11, 2016 in Digital Logic by jothee Veteran (99.8k points) | 1.7k views

+13 votes

2 answers

17

GATE2011-51
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration. If all the flip-flops were reset to $0$ at power on, what is the total number of distinct outputs (states) represented by $PQR$ generated by the counter? $3$ $4$ $5$ $6$

asked Apr 21, 2016 in Digital Logic by jothee Veteran (99.8k points) | 1.3k views

+17 votes

9 answers

18

GATE1993-6-3
Multiple choices can be correct. Mark all of them. For the initial state of 000, the function performed by the arrangement of the J-K flip-flops in figure is: Shift Register Mod- 3 Counter Mod- 6 Counter Mod- 2 Counter None of the above

asked Sep 20, 2015 in Digital Logic by jothee Veteran (99.8k points) | 2.2k views

+5 votes

1 answer

19

GATE1993-6.2
If the state machine described in figure, should have a stable state, the restriction on the inputs given by $a.b=1$ $a+b=1$ $\bar{a} + \bar{b} =0$ $\overline{a.b}=1$ $\overline{a+b} =1$

asked Sep 20, 2015 in Digital Logic by jothee Veteran (99.8k points) | 1.1k views

+1 vote

2 answers

20

what is 9 clock cycles what are output at q0 q1 q2?

asked Sep 4, 2015 in Digital Logic by Ravi Raaja (195 points) | 336 views

+5 votes

2 answers

21

ISRO2014-21, UGCNET-Dec2012-III-23, UGCNET-Dec2013-III-22

asked Jul 17, 2015 in Digital Logic by focus _GATE Boss (20.4k points) | 3.9k views

+16 votes

5 answers

22

GATE2005-IT-43
Which of the following input sequences will always generate a $1$ at the output $z$ at the end of the third cycle? A B C $0$ $0$ $0$ $1$ $0$ $1$ $1$ $1$ $1$ A B C $1$ $0$ $1$ $1$ $1$ $0$ $1$ $1$ $1$ A B C $0$ $1$ $1$ $1$ $0$ $1$ $1$ $1$ $1$ A B C $0$ $0$ $1$ $1$ $1$ $0$ $1$ $1$ $1$

asked Nov 4, 2014 in Digital Logic by Ishrat Jahan Boss (19.1k points) | 3.5k views

+14 votes

1 answer

23

GATE2005-IT-10
A two-way switch has three terminals a, b and c. In ON position (logic value 1), a is connected to b, and in OFF position, a is connected to c. Two of these two-way switches S1 and S2 are connected to a bulb as shown below. Which of the following ... true, will always result in the lighting of the bulb ? $S1.\overline{S2}$ $S1 + S2$ $\overline {S1\oplus S2}$ $S1 \oplus S2$

asked Nov 3, 2014 in Digital Logic by Ishrat Jahan Boss (19.1k points) | 1.2k views

+18 votes

2 answers

24

GATE2006-IT-36
The majority function is a Boolean function $f(x, y, z)$ that takes the value 1 whenever a majority of the variables $x,y,z$ are 1. In the circuit diagram for the majority function shown below, the logic gates for the boxes labeled P and Q are, respectively, XOR, AND XOR, XOR OR, OR OR, AND

asked Oct 31, 2014 in Digital Logic by Ishrat Jahan Boss (19.1k points) | 1.9k views

+16 votes

6 answers

25

GATE2007-IT-45
The line T in the following figure is permanently connected to the ground. Which of the following inputs (X1 X2 X3 X4) will detect the fault ? 0000 0111 1111 None of these

asked Oct 30, 2014 in Digital Logic by Ishrat Jahan Boss (19.1k points) | 2.1k views

+13 votes

5 answers

26

GATE2007-IT-40
What is the final value stored in the linear feedback shift register if the input is $101101$? $0110$ $1011$ $1101$ $1111$

asked Oct 30, 2014 in Digital Logic by Ishrat Jahan Boss (19.1k points) | 1.1k views

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