# Recent questions tagged circuit-output 0 votes
1 answer
1
Starting from a state of the state table given below find out the output sequence generated with an input sequence 01110010011. reduce the same table and repeat the same sequence with the given input sequence. Show that same output is obtained.
1 vote
1 answer
2
Reduce the number of states in the following state table and tabulate the reduced state table.
1 vote
0 answers
3
Starting from state 00 in the state transition diagram of the figure. Determine the state transitions and output sequence that will be generated when the input sequence of 010110111011110 is applied.
1 vote
0 answers
4
Derive the truth table for the output of each NOR gate in the given figure.
1 vote
2 answers
5
Verify the Circuit generates the Exclusive NOR Functions.
1 vote
1 answer
6
Determine the boolean function for the outputs F and G as a function of Four inputs A, B, C, And D.
0 votes
1 answer
7
Assume the operands are in 2’s Complement. To decrement A by 1, lines K,Cn and B should be : K = 1 , Cin = 1 , B = 1 K = 0 , Cin = 1 , B = 1 K = 0 , Cin = 1 , B = 0 K = 1 , Cin = 0 , B = 0
3 votes
0 answers
8
Consider the below Digital Circuit : The State Transition diagram on circuit is :
0 votes
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9
How the table is generated?
0 votes
2 answers
10
Assume the initial values of $K0$, $Q_0$ and $Q_1$ to be $1$. Which of the following state transition tables correctly correspond to the circuit given above? (Note: $Q_{kN}$ and $Q_{kN+1}$ ...
1 vote
2 answers
11
Answer is provided as C. But D should be the answer. Please confirm
1 vote
1 answer
12
I think all options are wrong.
0 votes
2 answers
13
What should be the answer... 9 votes
3 answers
14
In the diagram above, the inverter (NOT gate) and the AND-gates labeled $1$ and $2$ have delays of $9$, 10 and $12$ nanoseconds (ns), respectively. Wire delays are negligible. For certain values $a$ and $c$, together with certain transition of $b$, a glitch (spurious output) is ... , after which the output assumes its correct value. The duration of glitch is: $7$ $ns$ $9$ $ns$ $11$ $ns$ $13$ $ns$
4 votes
1 answer
15
Consider the synchronous sequential circuit in the below figure Given that the initial state of the circuit is $S_4,$ identify the set of states, which are not reachable.
1 vote
0 answers
16
1 vote
1 answer
17
4 votes
2 answers
18
2 votes
1 answer
19
Some please tell how to solve this question ?
0 votes
1 answer
20
\ can someone please help me to solve this with proper diagram?
4 votes
0 answers
21
Correct result ?
0 votes
2 answers
22
3 votes
0 answers
23
For the circuit shown below: For how many number of clock pulses for which $y_2$ is '1' ? $\text{A. 2 clock pulses}$ $\text{B. 3 clock pulses}$ $\text{C. 10 clock pulses}$ $\text{D. 6 clock pulses}$
4 votes
3 answers
24
In the circuit shown below, the propagation delay of each NOT gate is 2 nsec (2 nano sec), then the time period of generated square wave is – Please somebody explain the approach for this type of qestions