Recent questions tagged circuit-output

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Morris Mano Edition 3 Exercise 6 Question 15,16 (Page No. 254)
Starting from a state of the state table given below find out the output sequence generated with an input sequence 01110010011. reduce the same table and repeat the same sequence with the given input sequence. Show that same output is obtained.

asked Apr 4, 2019 in Digital Logic by ajaysoni1924 Boss (10.8k points) | 102 views

+1 vote

1 answer

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Morris Mano Edition 3 Exercise 6 Question 14 (Page No. 254)
Reduce the number of states in the following state table and tabulate the reduced state table.

asked Apr 4, 2019 in Digital Logic by ajaysoni1924 Boss (10.8k points) | 66 views

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Morris Mano Edition 3 Exercise 6 Question 13 (Page No. 254)
Starting from state 00 in the state transition diagram of the figure. Determine the state transitions and output sequence that will be generated when the input sequence of 010110111011110 is applied.

asked Apr 4, 2019 in Digital Logic by ajaysoni1924 Boss (10.8k points) | 36 views

+1 vote

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Morris Mano Edition 3 Exercise 4 Question 24 (Page No. 151)
Derive the truth table for the output of each NOR gate in the given figure.

asked Apr 2, 2019 in Digital Logic by ajaysoni1924 Boss (10.8k points) | 37 views

+1 vote

2 answers

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Morris Mano Edition 3 Exercise 4 Question 22 (Page No. 151)
Verify the Circuit generates the Exclusive NOR Functions.

asked Apr 2, 2019 in Digital Logic by ajaysoni1924 Boss (10.8k points) | 56 views

+1 vote

1 answer

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Morris Mano Edition 3 Exercise 4 Question 21 (Page No. 151)
Determine the boolean function for the outputs F and G as a function of Four inputs A, B, C, And D.

asked Apr 2, 2019 in Digital Logic by ajaysoni1924 Boss (10.8k points) | 37 views

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1 answer

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MadeEasy Subject Test 2019: Digital Logic - Circuit Output
Assume the operands are in 2’s Complement. To decrement A by 1, lines K,Cn and B should be : K = 1 , Cin = 1 , B = 1 K = 0 , Cin = 1 , B = 1 K = 0 , Cin = 1 , B = 0 K = 1 , Cin = 0 , B = 0

asked Jan 16, 2019 in Digital Logic by Na462 Loyal (7k points) | 181 views

+1 vote

0 answers

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MadeEasy Full Length Test 2018: Digital Logic - Circuit Output
Consider the below Digital Circuit : The State Transition diagram on circuit is :

asked Jan 13, 2019 in Digital Logic by Na462 Loyal (7k points) | 162 views

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9

MadeEasy Workbook: Digital Logic - Circuit Output
How the table is generated?

asked Dec 30, 2018 in Digital Logic by Jyoti Kumari97 (187 points) | 95 views

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1 answer

10

Gateforum Test Series: Digital Logic - Circuit Output
Answer is provided as C. But D should be the answer. Please confirm

asked Nov 7, 2018 in Digital Logic by Gupta731 Active (4.8k points) | 122 views

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1 answer

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Gateforum Test Series: Digital Logic - Circuit Output
I think all options are wrong.

asked Nov 7, 2018 in Digital Logic by Gupta731 Active (4.8k points) | 128 views

0 votes

2 answers

12

MadeEasy Workbook: Digital Logic - Circuit Output
What should be the answer...

asked Sep 26, 2018 in Digital Logic by anonymous | 65 views

+6 votes

2 answers

13

ISRO2018-9
In the diagram above, the inverter (NOT gate) and the AND-gates labeled $1$ and $2$ have delays of $9$, 10 and $12$ nanoseconds (ns), respectively. Wire delays are negligible. For certain values $a$ and $c$, together with certain transition of $b$, a glitch (spurious output ... which the output assumes its correct value. The duration of glitch is: $7$ $ns$ $9$ $ns$ $11$ $ns$ $13$ $ns$

asked Apr 22, 2018 in Digital Logic by Arjun Veteran (431k points) | 2.1k views

+2 votes

1 answer

14

GATE1996-24-b
Consider the synchronous sequential circuit in the below figure Given that the initial state of the circuit is S$_4$, identify the set of states, which are not reachable.

asked Feb 10, 2018 in Digital Logic by jothee Veteran (105k points) | 572 views

+1 vote

0 answers

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MadeEasy Full Length Test 2018: Digital Logic - Circuit Output

asked Jan 18, 2018 in Digital Logic by Abhishek Kumar Singh Junior (829 points) | 176 views

+1 vote

1 answer

16

MadeEasy Subject Test: Digital Logic - Circuit Output

asked Nov 27, 2017 in Digital Logic by charul Junior (823 points) | 130 views

+4 votes

2 answers

17

Virtual Gate Test Series: Digital Logic - Flip Flops

asked Nov 13, 2017 in Digital Logic by Manoja Rajalakshmi A Boss (11.6k points) | 297 views

+1 vote

1 answer

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MadeEasy Subject Test: Digital Logic - Circuit Output
Some please tell how to solve this question ?

asked Feb 2, 2017 in Digital Logic by shu (185 points) | 113 views

0 votes

1 answer

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MadeEasy Subject Test: Digital Logic - Circuit Output
\ can someone please help me to solve this with proper diagram?

asked Jan 23, 2017 in Digital Logic by S Ram Active (1.7k points) | 121 views

+3 votes

0 answers

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MadeEasy CBT 2017:Digital Logic - Circuit Output
Correct result ?

asked Jan 23, 2017 in Digital Logic by Vasu_gate2017 Active (1.1k points) | 1.2k views

0 votes

2 answers

21

MadeEasy Subject Test: Digital Logic - Circuit Output

asked Jan 11, 2017 in Digital Logic by Akanksha Kesarwani Junior (989 points) | 85 views

+2 votes

0 answers

22

MadeEasy Subject Test: Digital Logic - Circuit Output
For the circuit shown below: For how many number of clock pulses for which $y_2$ is '1' ? $ \text{A. 2 clock pulses} $ $ \text{B. 3 clock pulses} $ $ \text{C. 10 clock pulses} $ $ \text{D. 6 clock pulses} $

asked Jan 3, 2017 in Digital Logic by Sachin Mittal 1 Boss (17.9k points) | 171 views

+4 votes

3 answers

23

MadeEasy Subject Test: Digital Logic - Circuit Output
In the circuit shown below, the propagation delay of each NOT gate is 2 nsec (2 nano sec), then the time period of generated square wave is – Please somebody explain the approach for this type of qestions

asked Dec 26, 2016 in Digital Logic by Pankaj Joshi Active (2.7k points) | 331 views

+13 votes

1 answer

24

GATE1988-2-v
Three switching functions $f_1, \: f_2 \:$ and $f_3$ are expressed below as sum of minterms. $f_1 (w, x, y, z) = \sum \: 0, 1, 2, 3, 5, 12$ $f_2 (w, x, y, z) = \sum \: 0, 1, 2, 10, 13, 14, 15$ $f_3 (w, x, y, z) = \sum \: 2, 4, 5, 8$ Express the function $f$ realised by the circuit shown in the below figure as the sum of minterms (in decimal notation).

asked Dec 11, 2016 in Digital Logic by jothee Veteran (105k points) | 821 views

+3 votes

2 answers

25

GATE1989-4-ix
Provide short answers to the following questions: Explain the behaviour of the following logic circuit (Fig.4) with level input A and output B

asked Nov 30, 2016 in Digital Logic by makhdoom ghaya Boss (30.8k points) | 748 views

0 votes

2 answers

26

Simple Doubt in digital
Consider a simple OR gate with 2 inputs A and B, a ouput O which is taken back and reconnected to B as feedback. Now, A=0 and B=0 so O=0. If we give A=1 for like 1 sec , O=1 and now if we turn off the power from the circuit , 1.) will we get a infinite ... it and and O=1 (Assume a case when A=1,B=0 so O=1 , Now i quickly set A=0 , will this not automatically make B=1) ?

asked Nov 27, 2016 in Digital Logic by Aakash Das Junior (547 points) | 332 views

+6 votes

3 answers

27

GATE1990-3-i
Choose the correct alternatives (More than one may be correct). Two NAND gates having open collector outputs are tied together as shown in below figure. The logic function $Y,$ implemented by the circuit is, $Y=ABC + DE$ $Y=\overline{ABC + DE}$ $Y=ABC.DE$ $Y=\overline{ABC.DE}$

asked Nov 19, 2016 in Digital Logic by makhdoom ghaya Boss (30.8k points) | 1.3k views

+12 votes

2 answers

28

GATE1987-13-a
The below figure shows four D-type flip-flops connected as a shift register using a $XOR$ gate. The initial state and three subsequent states for three clock pulses are also given. State $Q_{A}$ $Q_{B}$ $Q_{C}$ $Q_{D}$ Initial $1$ $1$ $1$ $1$ After the first clock $0$ $1$ ... $0$ $0$ $1$ The state $Q_{A} Q_{B} Q_{C} Q_{D}$ after the fourth clock pulse is $0000$ $1111$ $1001$ $1000$

asked Nov 15, 2016 in Digital Logic by makhdoom ghaya Boss (30.8k points) | 920 views

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