menu
Login
Register
search
Log In
account_circle
Log In
Email or Username
Password
Remember
Log In
Register
I forgot my password
Register
Username
Email
Password
Register
add
Activity
Questions
Unanswered
Tags
Subjects
Users
Ask
Prev
Blogs
New Blog
Exams
GO Book for GATECSE 2022
Quick search syntax
tags
tag:apple
author
user:martin
title
title:apple
content
content:apple
exclude
-tag:apple
force match
+apple
views
views:100
score
score:10
answers
answers:2
is accepted
isaccepted:true
is closed
isclosed:true
Exact tag match
Recent Posts
GATE 2021 AIR 26 journey and some useful tips
A Short Guide to GATE
Seeking DRDO Scientist B previous year papers
STRATEGY TO EFFECTIVELY CREATE SHORT & MICRO NOTES FOR GATE EXAM AND BEST REVISION STRATEGY BY AIR-"152"
My Video Experience AIR-152 GATE_CS(Some More motivation)!!!!!!
Subjects
All categories
General Aptitude
(2.1k)
Engineering Mathematics
(8.5k)
Digital Logic
(3.1k)
Programming and DS
(5.2k)
Algorithms
(4.5k)
Theory of Computation
(6.3k)
Compiler Design
(2.2k)
Operating System
(4.7k)
Databases
(4.3k)
CO and Architecture
(3.5k)
Computer Networks
(4.3k)
Non GATE
(1.2k)
Others
(1.5k)
Admissions
(595)
Exam Queries
(838)
Tier 1 Placement Questions
(16)
Job Queries
(71)
Projects
(19)
Unknown Category
(1.1k)
Follow @gateoverflow
GATE Overflow
Recent questions tagged circuit-output
Recent Blog Comments
Thanks bro :) It has been quite the...
Wow! Awesome! Congratulations brother
It's one of the top University in Canada.
Hi falgun09, If you don't mind me asking, which...
That's great!
Network Sites
GO Mechanical
GO Electrical
GO Electronics
GO Civil
CSE Doubts
Recent questions tagged circuit-output
0
votes
1
answer
1
Morris Mano Edition 3 Exercise 6 Question 15,16 (Page No. 254)
Starting from a state of the state table given below find out the output sequence generated with an input sequence 01110010011. reduce the same table and repeat the same sequence with the given input sequence. Show that same output is obtained.
Starting from a state of the state table given below find out the output sequence generated with an input sequence 01110010011. reduce the same table and repeat the same sequence with the given input sequence. Show that same output is obtained.
asked
Apr 4, 2019
in
Digital Logic
ajaysoni1924
435
views
digital-logic
sequential-circuit
synchronous-asynchronous-circuits
circuit-output
1
vote
1
answer
2
Morris Mano Edition 3 Exercise 6 Question 14 (Page No. 254)
Reduce the number of states in the following state table and tabulate the reduced state table.
Reduce the number of states in the following state table and tabulate the reduced state table.
asked
Apr 4, 2019
in
Digital Logic
ajaysoni1924
1.2k
views
digital-logic
sequential-circuit
synchronous-asynchronous-circuits
circuit-output
1
vote
0
answers
3
Morris Mano Edition 3 Exercise 6 Question 13 (Page No. 254)
Starting from state 00 in the state transition diagram of the figure. Determine the state transitions and output sequence that will be generated when the input sequence of 010110111011110 is applied.
Starting from state 00 in the state transition diagram of the figure. Determine the state transitions and output sequence that will be generated when the input sequence of 010110111011110 is applied.
asked
Apr 4, 2019
in
Digital Logic
ajaysoni1924
812
views
digital-logic
sequential-circuit
circuit-output
synchronous-asynchronous-circuits
1
vote
0
answers
4
Morris Mano Edition 3 Exercise 4 Question 24 (Page No. 151)
Derive the truth table for the output of each NOR gate in the given figure.
Derive the truth table for the output of each NOR gate in the given figure.
asked
Apr 2, 2019
in
Digital Logic
ajaysoni1924
98
views
digital-logic
morris-mano
combinational-circuits
circuit-output
1
vote
2
answers
5
Morris Mano Edition 3 Exercise 4 Question 22 (Page No. 151)
Verify the Circuit generates the Exclusive NOR Functions.
Verify the Circuit generates the Exclusive NOR Functions.
asked
Apr 2, 2019
in
Digital Logic
ajaysoni1924
230
views
digital-logic
morris-mano
combinational-circuits
circuit-output
1
vote
1
answer
6
Morris Mano Edition 3 Exercise 4 Question 21 (Page No. 151)
Determine the boolean function for the outputs F and G as a function of Four inputs A, B, C, And D.
Determine the boolean function for the outputs F and G as a function of Four inputs A, B, C, And D.
asked
Apr 2, 2019
in
Digital Logic
ajaysoni1924
109
views
digital-logic
morris-mano
combinational-circuits
circuit-output
0
votes
1
answer
7
MadeEasy Subject Test 2019: Digital Logic - Circuit Output
Assume the operands are in 2’s Complement. To decrement A by 1, lines K,Cn and B should be : K = 1 , Cin = 1 , B = 1 K = 0 , Cin = 1 , B = 1 K = 0 , Cin = 1 , B = 0 K = 1 , Cin = 0 , B = 0
Assume the operands are in 2’s Complement. To decrement A by 1, lines K,Cn and B should be : K = 1 , Cin = 1 , B = 1 K = 0 , Cin = 1 , B = 1 K = 0 , Cin = 1 , B = 0 K = 1 , Cin = 0 , B = 0
asked
Jan 16, 2019
in
Digital Logic
Na462
592
views
digital-logic
circuit-output
madeeasy-testseries-2019
made-easy-test-series
3
votes
0
answers
8
MadeEasy Full Length Test 2018: Digital Logic - Circuit Output
Consider the below Digital Circuit : The State Transition diagram on circuit is :
Consider the below Digital Circuit : The State Transition diagram on circuit is :
asked
Jan 13, 2019
in
Digital Logic
Na462
323
views
digital-logic
circuit-output
made-easy-test-series
madeeasy-testseries-2019
0
votes
0
answers
9
MadeEasy Workbook: Digital Logic - Circuit Output
How the table is generated?
How the table is generated?
asked
Dec 30, 2018
in
Digital Logic
Jyoti Kumari97
201
views
made-easy-booklet
digital-logic
circuit-output
0
votes
2
answers
10
GO2019-FLT1-59
Assume the initial values of $K0$, $Q_0$ and $Q_1$ to be $1$. Which of the following state transition tables correctly correspond to the circuit given above? (Note: $Q_{kN}$ and $Q_{kN+1}$ ...
Assume the initial values of $K0$, $Q_0$ and $Q_1$ to be $1$. Which of the following state transition tables correctly correspond to the circuit given above? (Note: $Q_{kN}$ and $Q_{kN+1}$ ...
asked
Dec 27, 2018
in
Digital Logic
Ruturaj Mohanty
257
views
go2019-flt1
digital-circuits
circuit-output
digital-logic
1
vote
2
answers
11
Gateforum Test Series: Digital Logic - Circuit Output
Answer is provided as C. But D should be the answer. Please confirm
Answer is provided as C. But D should be the answer. Please confirm
asked
Nov 7, 2018
in
Digital Logic
Gupta731
265
views
digital-logic
gateforum-test-series
circuit-output
1
vote
1
answer
12
Gateforum Test Series: Digital Logic - Circuit Output
I think all options are wrong.
I think all options are wrong.
asked
Nov 7, 2018
in
Digital Logic
Gupta731
251
views
gateforum-test-series
digital-logic
circuit-output
0
votes
2
answers
13
MadeEasy Workbook: Digital Logic - Circuit Output
What should be the answer...
What should be the answer...
asked
Sep 26, 2018
in
Digital Logic
anonymous
127
views
digital-logic
circuit-output
made-easy-booklet
9
votes
3
answers
14
ISRO2018-9
In the diagram above, the inverter (NOT gate) and the AND-gates labeled $1$ and $2$ have delays of $9$, 10 and $12$ nanoseconds (ns), respectively. Wire delays are negligible. For certain values $a$ and $c$, together with certain transition of $b$, a glitch (spurious output ... which the output assumes its correct value. The duration of glitch is: $7$ $ns$ $9$ $ns$ $11$ $ns$ $13$ $ns$
In the diagram above, the inverter (NOT gate) and the AND-gates labeled $1$ and $2$ have delays of $9$, 10 and $12$ nanoseconds (ns), respectively. Wire delays are negligible. For certain values $a$ and $c$, together with certain transition of $b$, a glitch (spurious output) is ... , after which the output assumes its correct value. The duration of glitch is: $7$ $ns$ $9$ $ns$ $11$ $ns$ $13$ $ns$
asked
Apr 22, 2018
in
Digital Logic
Arjun
3.2k
views
isro2018
digital-logic
circuit-output
4
votes
1
answer
15
GATE1996-24-b
Consider the synchronous sequential circuit in the below figure Given that the initial state of the circuit is S$_4$, identify the set of states, which are not reachable.
Consider the synchronous sequential circuit in the below figure Given that the initial state of the circuit is S$_4$, identify the set of states, which are not reachable.
asked
Feb 10, 2018
in
Digital Logic
jothee
1.1k
views
gate1996
normal
digital-logic
circuit-output
1
vote
0
answers
16
MadeEasy Full Length Test 2018: Digital Logic - Circuit Output
asked
Jan 18, 2018
in
Digital Logic
Abhishek Kumar Singh
254
views
digital-logic
circuit-output
made-easy-test-series
1
vote
1
answer
17
MadeEasy Subject Test: Digital Logic - Circuit Output
asked
Nov 27, 2017
in
Digital Logic
charul
225
views
made-easy-test-series
digital-logic
circuit-output
sequential-circuit
4
votes
2
answers
18
Virtual Gate Test Series: Digital Logic - Flip Flops
asked
Nov 13, 2017
in
Digital Logic
Manoja Rajalakshmi A
700
views
digital-logic
sequential-circuit
flip-flop
circuit-output
virtual-gate-test-series
2
votes
1
answer
19
MadeEasy Subject Test: Digital Logic - Circuit Output
Some please tell how to solve this question ?
Some please tell how to solve this question ?
asked
Feb 2, 2017
in
Digital Logic
shu
202
views
digital-logic
made-easy-test-series
circuit-output
0
votes
1
answer
20
MadeEasy Subject Test: Digital Logic - Circuit Output
\ can someone please help me to solve this with proper diagram?
\ can someone please help me to solve this with proper diagram?
asked
Jan 23, 2017
in
Digital Logic
S Ram
175
views
made-easy-test-series
digital-logic
circuit-output
4
votes
0
answers
21
MadeEasy CBT 2017:Digital Logic - Circuit Output
Correct result ?
Correct result ?
asked
Jan 23, 2017
in
Digital Logic
Vasu_gate2017
1.4k
views
made-easy-test-series
cbt-2017
digital-logic
circuit-output
0
votes
2
answers
22
MadeEasy Subject Test: Digital Logic - Circuit Output
asked
Jan 11, 2017
in
Digital Logic
Akanksha Kesarwani
146
views
digital-logic
made-easy-test-series
circuit-output
3
votes
0
answers
23
MadeEasy Subject Test: Digital Logic - Circuit Output
For the circuit shown below: For how many number of clock pulses for which $y_2$ is '1' ? $ \text{A. 2 clock pulses} $ $ \text{B. 3 clock pulses} $ $ \text{C. 10 clock pulses} $ $ \text{D. 6 clock pulses} $
For the circuit shown below: For how many number of clock pulses for which $y_2$ is '1' ? $ \text{A. 2 clock pulses} $ $ \text{B. 3 clock pulses} $ $ \text{C. 10 clock pulses} $ $ \text{D. 6 clock pulses} $
asked
Jan 3, 2017
in
Digital Logic
Sachin Mittal 1
270
views
made-easy-test-series
digital-logic
circuit-output
4
votes
3
answers
24
MadeEasy Subject Test: Digital Logic - Circuit Output
In the circuit shown below, the propagation delay of each NOT gate is 2 nsec (2 nano sec), then the time period of generated square wave is – Please somebody explain the approach for this type of qestions
In the circuit shown below, the propagation delay of each NOT gate is 2 nsec (2 nano sec), then the time period of generated square wave is – Please somebody explain the approach for this type of qestions
asked
Dec 26, 2016
in
Digital Logic
Pankaj Joshi
609
views
made-easy-test-series
digital-logic
circuit-output
Page:
1
2
3
next »
...