Recent questions tagged circuit-output

Recent questions tagged circuit-output

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Morris Mano Edition 3 Exercise 6 Question 15,16 (Page No. 254)
Starting from a state of the state table given below find out the output sequence generated with an input sequence 01110010011. reduce the same table and repeat the same sequence with the given input sequence. Show that same output is obtained.

ajaysoni1924 asked in Digital Logic Apr 4, 2019

by ajaysoni1924

777 views

1 vote

1 answer

2

Morris Mano Edition 3 Exercise 6 Question 14 (Page No. 254)
Reduce the number of states in the following state table and tabulate the reduced state table.

ajaysoni1924 asked in Digital Logic Apr 4, 2019

by ajaysoni1924

2.5k views

1 vote

0 answers

3

Morris Mano Edition 3 Exercise 6 Question 13 (Page No. 254)
Starting from state 00 in the state transition diagram of the figure. Determine the state transitions and output sequence that will be generated when the input sequence of 010110111011110 is applied.

ajaysoni1924 asked in Digital Logic Apr 4, 2019

by ajaysoni1924

1.3k views

1 vote

0 answers

4

Morris Mano Edition 3 Exercise 4 Question 24 (Page No. 151)
Derive the truth table for the output of each NOR gate in the given figure.

ajaysoni1924 asked in Digital Logic Apr 2, 2019

by ajaysoni1924

168 views

1 vote

2 answers

5

Morris Mano Edition 3 Exercise 4 Question 22 (Page No. 151)
Verify the Circuit generates the Exclusive NOR Functions.

ajaysoni1924 asked in Digital Logic Apr 2, 2019

by ajaysoni1924

391 views

1 vote

1 answer

6

Morris Mano Edition 3 Exercise 4 Question 21 (Page No. 151)
Determine the boolean function for the outputs F and G as a function of Four inputs A, B, C, And D.

ajaysoni1924 asked in Digital Logic Apr 2, 2019

by ajaysoni1924

379 views

0 votes

1 answer

7

MadeEasy Subject Test 2019: Digital Logic - Circuit Output
Assume the operands are in 2’s Complement. To decrement A by 1, lines K,Cn and B should be : K = 1 , Cin = 1 , B = 1 K = 0 , Cin = 1 , B = 1 K = 0 , Cin = 1 , B = 0 K = 1 , Cin = 0 , B = 0

Na462 asked in Digital Logic Jan 16, 2019

by Na462

809 views

3 votes

0 answers

8

MadeEasy Full Length Test 2018: Digital Logic - Circuit Output
Consider the below Digital Circuit : The State Transition diagram on circuit is :

Na462 asked in Digital Logic Jan 13, 2019

by Na462

421 views

0 votes

0 answers

9

MadeEasy Workbook: Digital Logic - Circuit Output
How the table is generated?

Jyoti Kumari97 asked in Digital Logic Dec 30, 2018

by Jyoti Kumari97

265 views

0 votes

2 answers

10

GO2019-FLT1-59
Assume the initial values of $K0$, $Q_0$ and $Q_1$ to be $1$. Which of the following state transition tables correctly correspond to the circuit given above? (Note: $Q_{kN}$ and $Q_{kN+1}$ ...

Ruturaj Mohanty asked in Digital Logic Dec 27, 2018

by Ruturaj Mohanty

359 views

1 vote

2 answers

11

Gateforum Test Series: Digital Logic - Circuit Output
Answer is provided as C. But D should be the answer. Please confirm

Gupta731 asked in Digital Logic Nov 7, 2018

371 views

1 vote

1 answer

12

Gateforum Test Series: Digital Logic - Circuit Output
I think all options are wrong.

Gupta731 asked in Digital Logic Nov 7, 2018

376 views

0 votes

2 answers

13

MadeEasy Workbook: Digital Logic - Circuit Output
What should be the answer...

anonymous asked in Digital Logic Sep 26, 2018

by anonymous

203 views

10 votes

3 answers

14

ISRO2018-9
In the diagram above, the inverter (NOT gate) and the AND-gates labeled $1$ and $2$ have delays of $9$, 10 and $12$ nanoseconds (ns), respectively. Wire delays are negligible. For certain values $a$ and $c$, together with certain transition of $b$, a glitch (spurious output ... which the output assumes its correct value. The duration of glitch is: $7$ $ns$ $9$ $ns$ $11$ $ns$ $13$ $ns$

Arjun asked in Digital Logic Apr 22, 2018

by Arjun

3.7k views

4 votes

1 answer

15

GATE CSE 1996 | Question: 24-b
Consider the synchronous sequential circuit in the below figure Given that the initial state of the circuit is $S_4,$ identify the set of states, which are not reachable.

jothee asked in Digital Logic Feb 10, 2018

by jothee

1.4k views

1 vote

0 answers

16

MadeEasy Full Length Test 2018: Digital Logic - Circuit Output

Abhishek Kumar Singh asked in Digital Logic Jan 18, 2018

by Abhishek Kumar Singh

335 views

1 vote

1 answer

17

MadeEasy Subject Test: Digital Logic - Circuit Output

charul asked in Digital Logic Nov 27, 2017

by charul

306 views

4 votes

2 answers

18

Virtual Gate Test Series: Digital Logic - Flip Flops

Manoja Rajalakshmi A asked in Digital Logic Nov 13, 2017

by Manoja Rajalakshmi A

819 views

2 votes

2 answers

19

MadeEasy Subject Test: Digital Logic - Circuit Output
Some please tell how to solve this question ?

shu asked in Digital Logic Feb 2, 2017

by shu

323 views

0 votes

1 answer

20

MadeEasy Subject Test: Digital Logic - Circuit Output
\ can someone please help me to solve this with proper diagram?

S Ram asked in Digital Logic Jan 23, 2017

by S Ram

233 views

4 votes

0 answers

21

MadeEasy CBT 2017:Digital Logic - Circuit Output
Correct result ?

Vasu_gate2017 asked in Digital Logic Jan 23, 2017

by Vasu_gate2017

1.5k views

0 votes

2 answers

22

MadeEasy Subject Test: Digital Logic - Circuit Output

Akanksha Kesarwani asked in Digital Logic Jan 11, 2017

by Akanksha Kesarwani

208 views

3 votes

0 answers

23

MadeEasy Subject Test: Digital Logic - Circuit Output
For the circuit shown below: For how many number of clock pulses for which $y_2$ is '1' ? $ \text{A. 2 clock pulses} $ $ \text{B. 3 clock pulses} $ $ \text{C. 10 clock pulses} $ $ \text{D. 6 clock pulses} $

Sachin Mittal 1 asked in Digital Logic Jan 3, 2017

by Sachin Mittal 1

332 views

4 votes

3 answers

24

MadeEasy Subject Test: Digital Logic - Circuit Output
In the circuit shown below, the propagation delay of each NOT gate is 2 nsec (2 nano sec), then the time period of generated square wave is – Please somebody explain the approach for this type of qestions

Pankaj Joshi asked in Digital Logic Dec 26, 2016

by Pankaj Joshi

869 views

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