Recent questions tagged circuit-output

In the circuit shown below, the propagation delay of each NOT gate is 2 nsec (2 nano sec), then the time period of generated square wave is –Please somebody explain the a...

Three switching functions $f_1, \: f_2 \:$ and $f_3$ are expressed below as sum of minterms.$f_1 (w, x, y, z) = \sum \: 0, 1, 2, 3, 5, 12$$f_2 (w, x, y, z) = \sum \: 0, 1...

Explain the behaviour of the following logic circuit with level input $A$ and output $B$.

Choose the correct alternatives (More than one may be correct).Two NAND gates having open collector outputs are tied together as shown in below figure.The logic function ...

The below figure shows four $\text{D}$-type flip-flops connected as a shift register using a $\text{XOR}$ gate. The initial state and three subsequent states for three cl...

The output $F$ of the below multiplexer circuit can be represented by$AB+B\bar{C}+\bar{C}A+\bar{B}\bar{C}$$A\oplus B\oplus C$$A \oplus B$$\bar{A} \bar{B} C+ \bar{A} B \ba...

The following expression was to be realized using 2-input AND and OR gates, but by mistake all 2-input AND gates were taken as 2-input NAND gates,$$(a.b).c + (\bar a.c).d...

A sequential circuit has three D flip-flops $A, B, C$ and one input $X$. The circuit is described by the following input equations:$$D_A = (B\bar C + \bar BC ) X + (BC + ...

What will be output of the following logic diagram ?x $\text{OR}$ yx $\text{AND}$ yx $\text{XOR}$ yx $\text{XNOR}$ y

The circuit given in the figure below isAn oscillating circuit and its output is square waveThe one whose output remains stable in $\text{‘1'}$ stateThe one having output...

Consider the following gate networkWhich one of the following gates is redundant?Gate No. $1$Gate No. $2$Gate No. $3$Gate No. $4$

Consider the logic circuit given below.The inverter, AND and OR gates have delays of $6, 10$ and $11$ nanoseconds respectively. Assuming that wire delays are negligible, ...

Consider the logic circuit given below:$\text{Q =}$ __________?$\overline{\text{A}} \text{C} + \text{B} \overline{\text{C}} +\text{CD}$$\text{ABC} + \overline{\text{C}} \...

The output $\text{Y}$ of the given circuit$1$$0$$\text{X}$$\text{X}'$

The logic operations of two combinational circuits in Figure-I and Figure -II areentirely differentidenticalcomplementarydual

In the given network of AND and OR gates $f$ can be written as$\text{X}_0\text{X}_1\text{X}_2 \dots \text{X}_n + \text{X}_1\text{X}_2 \dots \text{X}_n + \text{X}_2\text{X...

The circuit shown in the following figure realizes the function.$(\overline{A+B}+C)(\overline{D}\;\overline{E})$$(\overline{A+B}+C)(D\overline{E})$$(A+ \overline{B+C})(\o...

Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.If all the flip-flops were reset to $0$ at power on, what...

Consider the logical circuit shown below:If initially ABC = 000 then after how many clock pulses the circuit will reach its initial stage?a) 5b) 6c) 7d) 8

For the initial state of $000$, the function performed by the arrangement of the $\text{J-K}$ flip-flops in figure is:Shift Register$\text{Mod- 3}$ Counter$\text{Mod- 6}$...

If the state machine described in figure should have a stable state, the restriction on the inputs is given by$a.b=1$$a+b=1$$\bar{a} + \bar{b} =0$$\overline{a.b}=1$$\over...

What are the final values of $\text{Q}_1$ and $\text{Q}_0$ after $4$ clock cycles, if initial values are $00$ in the sequential circuit shown below:$11$$01$$10$$00$

A two-way switch has three terminals $a, b$ and $c.$ In ON position (logic value $1$), $a$ is connected to $b,$ and in OFF position, $a$ is connected to $c$. Two of these...

The majority function is a Boolean function $f(x, y, z)$ that takes the value $1$ whenever a majority of the variables $x,y,z$ are $1.$ In the circuit diagram for the maj...