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Recent questions tagged circuitoutput
+14
votes
2
answers
1
GATE19936.1
Identify the logic function performed by the circuit shown in figure. exclusive OR exclusive NOR NAND NOR None of the above
asked
Sep 30, 2014
in
Digital Logic
by
Kathleen

2.7k
views
gate1993
digitallogic
circuitoutput
normal
+15
votes
2
answers
2
GATE19975.5
Consider a logic circuit shown in figure below. The functions $f_1, f_2 \text{ and } f$ (in canonical sum of products form in decimal notation) are : $f_1 (w, x, y, z) = \sum 8, 9, 10$ $f_2 (w, x, y, z) = \sum 7, 8, 12, 13, 14, 15$ $f (w, x, y, z) = \sum 8, 9$ The function $f_3$ is $\sum 9, 10$ $\sum 9$ $\sum 1, 8, 9$ $\sum 8, 10, 15$
asked
Sep 30, 2014
in
Digital Logic
by
Kathleen

1.9k
views
gate1997
digitallogic
circuitoutput
normal
+39
votes
9
answers
3
GATE201032
In the sequential circuit shown below, if the initial value of the output $Q_1Q_0$ is $00$. What are the next four values of $Q_1Q_0$? $11$, $10$, $01$, $00$ $10$, $11$, $01$, $00$ $10$, $00$, $01$, $11$ $11$, $10$, $00$, $01$
asked
Sep 29, 2014
in
Digital Logic
by
jothee

8.9k
views
gate2010
digitallogic
circuitoutput
normal
+20
votes
4
answers
4
GATE201031
What is the boolean expression for the output $f$ of the combinational logic circuit of NOR gates given below? $\overline{Q+R}$ $\overline{P+Q}$ $\overline{P+R}$ $\overline{P+Q+R}$
asked
Sep 29, 2014
in
Digital Logic
by
jothee

4.4k
views
gate2010
digitallogic
circuitoutput
normal
+16
votes
2
answers
5
GATE20109
The Boolean expression of the output $f$ of the multiplexer shown below is $\overline {P \oplus Q \oplus R}$ $P \oplus Q \oplus R$ $P+Q+R$ $\overline{P+Q+R}$
asked
Sep 29, 2014
in
Digital Logic
by
jothee

3.1k
views
gate2010
digitallogic
circuitoutput
easy
+20
votes
4
answers
6
GATE201150
Consider the following circuit involving three Dtype flipflops used in a certain type of counter configuration. If at some instance prior to the occurrence of the clock edge, $P, Q$ and $R$ have a value $0$, $1$ and $0$ respectively, what shall be the value of $PQR$ after the clock edge? $000$ $001$ $010$ $011$
asked
Sep 29, 2014
in
Digital Logic
by
jothee

3.9k
views
gate2011
digitallogic
circuitoutput
flipflop
normal
+20
votes
5
answers
7
GATE2014345
The above synchronous sequential circuit built using JK flipflops is initialized with $Q_2Q_1Q_0 = 000$. The state sequence for this circuit for the next $3$ clock cycles is $001, 010, 011$ $111, 110, 101$ $100, 110, 111$ $100, 011, 001$
asked
Sep 28, 2014
in
Digital Logic
by
jothee

5k
views
gate20143
digitallogic
circuitoutput
normal
+19
votes
3
answers
8
GATE19992.8
Consider the circuit shown below. In a certain steady state, the line $Y$ is at $'1'$. What are the possible values of $A, B$ and $C$ in this state? $A=0, B=0, C=1$ $A=0, B=1, C=1$ $A=1, B=0, C=1$ $A=1, B=1, C=1$
asked
Sep 24, 2014
in
Digital Logic
by
Kathleen

2.8k
views
gate1999
digitallogic
circuitoutput
normal
+21
votes
3
answers
9
GATE200564
Consider the following circuit: The flipflops are positive edge triggered D FFs. Each state is designated as a twobit string $Q_0Q_1$. Let the initial state be 00. The state transition sequence is
asked
Sep 23, 2014
in
Digital Logic
by
Kathleen

3.3k
views
gate2005
digitallogic
circuitoutput
+12
votes
3
answers
10
GATE200515
Consider the following circuit. Which one of the following is TRUE? $f$ is independent of $x$ $f$ is independent of $y$ $f$ is independent of $z$ None of $x, y, z$ is redundant
asked
Sep 23, 2014
in
Digital Logic
by
Kathleen

2.6k
views
gate2005
digitallogic
circuitoutput
normal
+24
votes
5
answers
11
GATE200637
Consider the circuit in the diagram. The $\oplus$ operator represents ExOR. The D flipflops are initialized to zeroes (cleared). The following data: $100110000$ is supplied to the “data” terminal in nine clock cycles. After that the values of $q_{2}q_{1}q_{0}$ are: $000$ $001$ $010$ $101$
asked
Sep 22, 2014
in
Digital Logic
by
Rucha Shelke

4.2k
views
gate2006
digitallogic
circuitoutput
easy
+23
votes
2
answers
12
GATE200635
Consider the circuit above. Which one of the following options correctly represents $f\left(x,y,z\right)$ $x\bar{z}+xy+\bar{y}z$ $x\bar{z}+xy+\overline{yz}$ $xz+xy+\overline{yz}$ $xz+x\bar{y}+\bar{y}z$
asked
Sep 22, 2014
in
Digital Logic
by
Rucha Shelke

3.5k
views
gate2006
digitallogic
circuitoutput
normal
+51
votes
6
answers
13
GATE200736
The control signal functions of a $4$$bit$ binary counter are given below (where $X$ ... cycles through the following sequence: $0, 3, 4$ $0, 3, 4, 5$ $0, 1, 2, 3, 4$ $0, 1, 2, 3, 4, 5$
asked
Sep 22, 2014
in
Digital Logic
by
Kathleen

8.4k
views
gate2007
digitallogic
circuitoutput
normal
+29
votes
5
answers
14
GATE200461
Consider the partial implementation of a 2bit counter using T flipflops following the sequence 02310, as shown below. To complete the circuit, the input X should be $Q_2^c$ $Q_2 + Q_1$ $\left(Q_1 + Q_2\right)^c$ $Q_1 \oplus Q_2$
asked
Sep 19, 2014
in
Digital Logic
by
Kathleen

5.8k
views
gate2004
digitallogic
circuitoutput
normal
+46
votes
5
answers
15
GATE20068
You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flipflops) will delay the phase of $f$ by $180°$?
asked
Sep 17, 2014
in
Digital Logic
by
Rucha Shelke

7.7k
views
gate2006
digitallogic
normal
circuitoutput
+29
votes
2
answers
16
GATE20022.2
Consider the following multiplexer where $I0, I1, I2, I3$ are four data input lines selected by two address line combinations $A1A0=00,01,10,11$ respectively and $f$ is the output of the multiplexor. EN is the Enable input. The function $f(x,y,z)$ implemented by the above circuit is $xyz'$ $xy + z$ $x + y$ None of the above
asked
Sep 16, 2014
in
Digital Logic
by
Kathleen

4.2k
views
gate2002
digitallogic
circuitoutput
normal
+41
votes
3
answers
17
GATE200221
Consider the following logic circuit whose inputs are functions $f_1, f_2, f_3$ and output is $f$ Given that $f_1(x,y,z) = \Sigma (0,1,3,5)$ $f_2(x,y,z) = \Sigma (6,7),$ and $f(x,y,z) = \Sigma (1,4,5).$ $f_3$ is $\Sigma (1,4,5)$ $\Sigma (6,7)$ $\Sigma (0,1,3,5)$ None of the above
asked
Sep 16, 2014
in
Digital Logic
by
Kathleen

4.9k
views
gate2002
digitallogic
normal
canonicalnormalform
circuitoutput
+41
votes
5
answers
18
GATE20012.8
Consider the following circuit with initial state $Q_0 = Q_1 = 0$. The D Flipflops are positive edged triggered and have set up times 20 nanosecond and hold times $0.$ Consider the following timing diagrams of X and C. The clock period of $C \geq 40$ nanosecond. Which one is the correct plot of Y?
asked
Sep 15, 2014
in
Digital Logic
by
Kathleen

7.9k
views
gate2001
digitallogic
circuitoutput
normal
+30
votes
5
answers
19
GATE20002.12
The following arrangement of masterslave flip flops has the initial state of $P, Q$ as $0, 1$ (respectively). After three clock cycles the output state $P, Q$ is (respectively), $1, 0$ $1, 1$ $0, 0$ $0, 1$
asked
Sep 15, 2014
in
Digital Logic
by
Kathleen

4.5k
views
gate2000
digitallogic
circuitoutput
normal
flipflop
+20
votes
1
answer
20
GATE19915a
Analyse the circuit in Fig below and complete the following table ${\begin{array}{ccc}\hline \textbf{a}& \textbf{b}& \bf{ Q_n} \\\hline 0&0\\\ 0&1 \\ 1&0 \\ 1&1 \\ \hline \end{array}}$
asked
Sep 13, 2014
in
Digital Logic
by
Kathleen

1.5k
views
gate1991
digitallogic
normal
circuitoutput
+3
votes
1
answer
21
GATE199101,i
asked
Sep 12, 2014
in
Others
by
Kathleen

546
views
gate1991
digitallogic
circuitoutput
normal
outofsyllabusnow
+36
votes
3
answers
22
GATE200562
Consider the following circuit involving a positive edge triggered D FF. Consider the following timing diagram. Let $A_{i}$ represents the logic level on the line a in the ith clock period. Let $A'$ represent the compliment of $A$. The correct output sequence on $Y$ over the clock periods $1$ through $5$ is: ... $A_{1} A_{2} A_{2}' A_{3} A_{4}$ $A_{1} A_{2}' A_{3} A_{4} A_{5}'$
asked
Sep 3, 2014
in
Digital Logic
by
Isha Karn

7.1k
views
gate2005
digitallogic
circuitoutput
normal
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