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Recent questions tagged circuit-output
7
votes
1
answer
61
ISRO2008-26
The logic operations of two combinational circuits in Figure-I and Figure -II are entirely different identical complementary dual
The logic operations of two combinational circuits in Figure-I and Figure -II areentirely differentidenticalcomplementarydual
go_editor
4.5k
views
go_editor
asked
Jun 12, 2016
Digital Logic
isro2008
digital-logic
circuit-output
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–
5
votes
2
answers
62
ISRO2008-12
In the given network of AND and OR gates $f$ can be written as $\text{X}_0\text{X}_1\text{X}_2 \dots \text{X}_n + \text{X}_1\text{X}_2 \dots \text{X}_n + \text{X}_2\text{X}_3 \dots \text{X}_n + \dots + \text{X}_n$ ...
In the given network of AND and OR gates $f$ can be written as$\text{X}_0\text{X}_1\text{X}_2 \dots \text{X}_n + \text{X}_1\text{X}_2 \dots \text{X}_n + \text{X}_2\text{X...
go_editor
4.9k
views
go_editor
asked
Jun 11, 2016
Digital Logic
isro2008
digital-logic
circuit-output
+
–
6
votes
2
answers
63
ISRO2007-02
The circuit shown in the following figure realizes the function. $(\overline{A+B}+C)(\overline{D}\;\overline{E})$ $(\overline{A+B}+C)(D\overline{E})$ $(A+ \overline{B+C})(\overline{D}E)$ $(A+ B+\overline{C})(\overline{D} \;\overline{E})$
The circuit shown in the following figure realizes the function.$(\overline{A+B}+C)(\overline{D}\;\overline{E})$$(\overline{A+B}+C)(D\overline{E})$$(A+ \overline{B+C})(\o...
go_editor
5.2k
views
go_editor
asked
Jun 5, 2016
Digital Logic
isro2007
digital-logic
digital-circuits
circuit-output
+
–
25
votes
2
answers
64
GATE CSE 2011 | Question: 51
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration. If all the flip-flops were reset to $0$ at power on, what is the total number of distinct outputs (states) represented by $PQR$ generated by the counter? $3$ $4$ $5$ $6$
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.If all the flip-flops were reset to $0$ at power on, what...
go_editor
7.4k
views
go_editor
asked
Apr 21, 2016
Digital Logic
gatecse-2011
digital-logic
circuit-output
normal
+
–
1
votes
1
answer
65
MadeEasy Test Series: Digital Logic - Circuit Output
Consider the logical circuit shown below: If initially ABC = 000 then after how many clock pulses the circuit will reach its initial stage? a) 5 b) 6 c) 7 d) 8
Consider the logical circuit shown below:If initially ABC = 000 then after how many clock pulses the circuit will reach its initial stage?a) 5b) 6c) 7d) 8
Sandeep Singh
871
views
Sandeep Singh
asked
Jan 10, 2016
Digital Logic
digital-logic
circuit-output
made-easy-test-series
+
–
33
votes
9
answers
66
GATE CSE 1993 | Question: 6-3
For the initial state of $000$, the function performed by the arrangement of the $\text{J-K}$ flip-flops in figure is: Shift Register $\text{Mod- 3}$ Counter $\text{Mod- 6}$ Counter $\text{Mod- 2}$ Counter None of the above
For the initial state of $000$, the function performed by the arrangement of the $\text{J-K}$ flip-flops in figure is:Shift Register$\text{Mod- 3}$ Counter$\text{Mod- 6}$...
go_editor
12.5k
views
go_editor
asked
Sep 20, 2015
Digital Logic
gate1993
digital-logic
sequential-circuit
flip-flop
digital-counter
circuit-output
multiple-selects
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–
19
votes
2
answers
67
GATE CSE 1993 | Question: 6.2
If the state machine described in figure should have a stable state, the restriction on the inputs is given by $a.b=1$ $a+b=1$ $\bar{a} + \bar{b} =0$ $\overline{a.b}=1$ $\overline{a+b} =1$
If the state machine described in figure should have a stable state, the restriction on the inputs is given by$a.b=1$$a+b=1$$\bar{a} + \bar{b} =0$$\overline{a.b}=1$$\over...
go_editor
7.0k
views
go_editor
asked
Sep 20, 2015
Digital Logic
gate1993
digital-logic
normal
circuit-output
sequential-circuit
+
–
10
votes
3
answers
68
ISRO2014-21, UGCNET-Dec2012-III: 23, UGCNET-Dec2013-III: 22
What are the final values of $\text{Q}_1$ and $\text{Q}_0$ after $4$ clock cycles, if initial values are $00$ in the sequential circuit shown below: $11$ $01$ $10$ $00$
What are the final values of $\text{Q}_1$ and $\text{Q}_0$ after $4$ clock cycles, if initial values are $00$ in the sequential circuit shown below:$11$$01$$10$$00$
focus _GATE
12.4k
views
focus _GATE
asked
Jul 17, 2015
Digital Logic
isro2014
digital-logic
circuit-output
ugcnetcse-dec2012-paper3
ugcnetcse-dec2013-paper3
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37
votes
5
answers
69
GATE IT 2005 | Question: 43
Which of the following input sequences will always generate a $1$ at the output $z$ ...
Which of the following input sequences will always generate a $1$ at the output $z$ at the end of the third cycle?$\begin{array}{|l|l|}\hline \textbf{A} & \textbf{B} & \t...
Ishrat Jahan
15.1k
views
Ishrat Jahan
asked
Nov 3, 2014
Digital Logic
gateit-2005
digital-logic
circuit-output
normal
+
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26
votes
1
answer
70
GATE IT 2005 | Question: 10
A two-way switch has three terminals $a, b$ and $c.$ In ON position (logic value $1$), $a$ is connected to $b,$ and in OFF position, $a$ is connected to $c$. Two of these two-way switches $S1$ and $S2$ are connected to a bulb as shown below. ... true, will always result in the lighting of the bulb ? $S1.\overline{S2}$ $S1 + S2$ $\overline {S1\oplus S2}$ $S1 \oplus S2$
A two-way switch has three terminals $a, b$ and $c.$ In ON position (logic value $1$), $a$ is connected to $b,$ and in OFF position, $a$ is connected to $c$. Two of these...
Ishrat Jahan
6.3k
views
Ishrat Jahan
asked
Nov 3, 2014
Digital Logic
gateit-2005
digital-logic
circuit-output
normal
+
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33
votes
3
answers
71
GATE IT 2006 | Question: 36
The majority function is a Boolean function $f(x, y, z)$ that takes the value $1$ whenever a majority of the variables $x,y,z$ are $1.$ In the circuit diagram for the majority function shown below, the logic gates for the boxes labeled $P$ and $Q$ are, ... $\textsf{XOR}, \textsf{XOR}$ $\textsf{OR}, \textsf{OR}$ $\textsf{OR}, \textsf{AND}$
The majority function is a Boolean function $f(x, y, z)$ that takes the value $1$ whenever a majority of the variables $x,y,z$ are $1.$ In the circuit diagram for the maj...
Ishrat Jahan
9.7k
views
Ishrat Jahan
asked
Oct 31, 2014
Digital Logic
gateit-2006
digital-logic
circuit-output
normal
+
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38
votes
8
answers
72
GATE IT 2007 | Question: 45
The line $T$ in the following figure is permanently connected to the ground. Which of the following inputs $(X_1 X_2 X_3 X_4)$ will detect the fault ? $0000$ $0111$ $1111$ None of these
The line $T$ in the following figure is permanently connected to the ground.Which of the following inputs $(X_1 X_2 X_3 X_4)$ will detect the fault ?$0000$$0111$$1111$Non...
Ishrat Jahan
12.1k
views
Ishrat Jahan
asked
Oct 29, 2014
Digital Logic
gateit-2007
digital-logic
circuit-output
normal
+
–
23
votes
6
answers
73
GATE IT 2007 | Question: 40
What is the final value stored in the linear feedback shift register if the input is $101101$? $0110$ $1011$ $1101$ $1111$
What is the final value stored in the linear feedback shift register if the input is $101101$?$0110$$1011$$1101$$1111$
Ishrat Jahan
6.4k
views
Ishrat Jahan
asked
Oct 29, 2014
Digital Logic
gateit-2007
digital-logic
circuit-output
normal
+
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30
votes
2
answers
74
GATE IT 2007 | Question: 38
The following expression was to be realized using $2$-input AND and OR gates. However, during the fabrication all $2$-input AND gates were mistakenly substituted by $2$-input NAND gates. $(a.b).c + (a'.c).d + (b.c).d + a. d$ What is the function finally ... $a' + b' + c' + d'$ $a' + b + c' + d'$ $a' + b' + c + d'$
The following expression was to be realized using $2$-input AND and OR gates. However, during the fabrication all $2$-input AND gates were mistakenly substituted by $2$-i...
Ishrat Jahan
6.2k
views
Ishrat Jahan
asked
Oct 29, 2014
Digital Logic
gateit-2007
digital-logic
circuit-output
normal
+
–
30
votes
2
answers
75
GATE IT 2008 | Question: 9
What Boolean function does the circuit below realize? $xz + \bar{x}\bar{z}$ $x\bar{z} + \bar{x}{z}$ $\bar{x}\bar{y} + {y}{z}$ $xy + \bar{y}\bar{z}$
What Boolean function does the circuit below realize?$xz + \bar{x}\bar{z}$$x\bar{z} + \bar{x}{z}$$\bar{x}\bar{y} + {y}{z}$$xy + \bar{y}\bar{z}$
Ishrat Jahan
9.1k
views
Ishrat Jahan
asked
Oct 27, 2014
Digital Logic
gateit-2008
digital-logic
circuit-output
decoder
normal
+
–
18
votes
2
answers
76
GATE CSE 1996 | Question: 24-a
Consider the synchronous sequential circuit in the below figure Draw a state diagram, which is implemented by the circuit. Use the following names for the states corresponding to the values of flip-flops as given below. ... $} \\\hline \end{array}$
Consider the synchronous sequential circuit in the below figureDraw a state diagram, which is implemented by the circuit. Use the following names for the states correspon...
Kathleen
6.4k
views
Kathleen
asked
Oct 9, 2014
Digital Logic
gate1996
digital-logic
circuit-output
normal
descriptive
+
–
24
votes
2
answers
77
GATE CSE 1996 | Question: 2.22
Consider the circuit in figure. $f$ implements $\overline{A} \overline{B}C + \overline{A}B \overline{C} + ABC$ $A + B + C$ $A \oplus B \oplus C$ $AB + BC + CA$
Consider the circuit in figure. $f$ implements$\overline{A} \overline{B}C + \overline{A}B \overline{C} + ABC$$A + B + C$$A \oplus B \oplus C$$AB + BC + CA$
Kathleen
8.4k
views
Kathleen
asked
Oct 9, 2014
Digital Logic
gate1996
digital-logic
circuit-output
easy
multiplexer
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–
43
votes
5
answers
78
GATE CSE 1996 | Question: 2.21
Consider the circuit in below figure which has a four bit binary number $b_3b_2b_1b_0$ as input and a five bit binary number, $d_4d_3d_2d_1d_0$ as output. Binary to Hex conversion Binary to BCD conversion Binary to Gray code conversion Binary to $radix-12$ conversion
Consider the circuit in below figure which has a four bit binary number $b_3b_2b_1b_0$ as input and a five bit binary number, $d_4d_3d_2d_1d_0$ as output.Binary to Hex co...
Kathleen
13.9k
views
Kathleen
asked
Oct 9, 2014
Digital Logic
gate1996
digital-logic
circuit-output
normal
+
–
25
votes
2
answers
79
GATE CSE 1994 | Question: 11
Find the contents of the flip-flop $Q_2, Q_1$ and $Q_0$ in the circuit of figure, after giving four clock pulses to the clock terminal. Assume $Q_2Q_1Q_0=000$ initially.
Find the contents of the flip-flop $Q_2, Q_1$ and $Q_0$ in the circuit of figure, after giving four clock pulses to the clock terminal. Assume $Q_2Q_1Q_0=000$ initially.
Kathleen
5.9k
views
Kathleen
asked
Oct 5, 2014
Digital Logic
gate1994
digital-logic
sequential-circuit
digital-counter
circuit-output
normal
descriptive
+
–
25
votes
1
answer
80
GATE CSE 1994 | Question: 1.8
The logic expression for the output of the circuit shown in figure below is: $\overline{AC} + \overline{BC} +CD$ $\overline{A}C + \overline{B}C + CD$ $ABC +\overline {C}\; \overline{D}$ $\overline{A}\; \overline{B} + \overline{B}\; \overline{C} +CD$
The logic expression for the output of the circuit shown in figure below is:$\overline{AC} + \overline{BC} +CD$$\overline{A}C + \overline{B}C + CD$$ABC +\overline {C}\; \...
Kathleen
6.5k
views
Kathleen
asked
Oct 4, 2014
Digital Logic
gate1994
digital-logic
circuit-output
normal
+
–
20
votes
1
answer
81
GATE CSE 1993 | Question: 19
A control algorithm is implemented by the NAND – gate circuitry given in figure below, where $A$ and $B$ are state variable implemented by $D$ flip-flops, and $P$ is control input. Develop the state transition table for this controller.
A control algorithm is implemented by the NAND – gate circuitry given in figure below, where $A$ and $B$ are state variable implemented by $D$ flip-flops, and $P$ is co...
Kathleen
3.0k
views
Kathleen
asked
Sep 29, 2014
Digital Logic
gate1993
digital-logic
sequential-circuit
flip-flop
circuit-output
normal
descriptive
+
–
21
votes
2
answers
82
GATE CSE 1993 | Question: 6.1
Identify the logic function performed by the circuit shown in figure. exclusive OR exclusive NOR NAND NOR None of the above
Identify the logic function performed by the circuit shown in figure. exclusive ORexclusive NORNANDNORNone of the above
Kathleen
9.0k
views
Kathleen
asked
Sep 29, 2014
Digital Logic
gate1993
digital-logic
combinational-circuit
circuit-output
normal
+
–
22
votes
1
answer
83
GATE CSE 1997 | Question: 5.5
Consider a logic circuit shown in figure below. The functions $f_1, f_2 \text{ and } f$ (in canonical sum of products form in decimal notation) are : $f_1 (w, x, y, z) = \sum 8, 9, 10$ $f_2 (w, x, y, z) = \sum 7, 8, 12, 13, 14, 15$ $f (w, x, y, z) = \sum 8, 9$ The function $f_3$ is $\sum 9, 10$ $\sum 9$ $\sum 1, 8, 9$ $\sum 8, 10, 15$
Consider a logic circuit shown in figure below. The functions $f_1, f_2 \text{ and } f$ (in canonical sum of products form in decimal notation) are :$f_1 (w, x, y, z) = \...
Kathleen
6.1k
views
Kathleen
asked
Sep 29, 2014
Digital Logic
gate1997
digital-logic
circuit-output
normal
+
–
53
votes
10
answers
84
GATE CSE 2010 | Question: 32
In the sequential circuit shown below, if the initial value of the output $Q_1Q_0$ is $00$. What are the next four values of $Q_1Q_0$? $11$, $10$, $01$, $00$ $10$, $11$, $01$, $00$ $10$, $00$, $01$, $11$ $11$, $10$, $00$, $01$
In the sequential circuit shown below, if the initial value of the output $Q_1Q_0$ is $00$. What are the next four values of $Q_1Q_0$? $11$, $10$, $01$, $00$$10$, $11$, $...
go_editor
30.5k
views
go_editor
asked
Sep 29, 2014
Digital Logic
gatecse-2010
digital-logic
circuit-output
normal
+
–
30
votes
4
answers
85
GATE CSE 2010 | Question: 31
What is the boolean expression for the output $f$ of the combinational logic circuit of NOR gates given below? $\overline{Q+R}$ $\overline{P+Q}$ $\overline{P+R}$ $\overline{P+Q+R}$
What is the boolean expression for the output $f$ of the combinational logic circuit of NOR gates given below?$\overline{Q+R}$$\overline{P+Q}$$\overline{P+R}$$\overline{P...
go_editor
11.5k
views
go_editor
asked
Sep 29, 2014
Digital Logic
gatecse-2010
digital-logic
circuit-output
normal
+
–
24
votes
2
answers
86
GATE CSE 2010 | Question: 9
The Boolean expression of the output $f$ of the multiplexer shown below is $\overline {P \oplus Q \oplus R}$ $P \oplus Q \oplus R$ $P+Q+R$ $\overline{P+Q+R}$
The Boolean expression of the output $f$ of the multiplexer shown below is$\overline {P \oplus Q \oplus R}$$P \oplus Q \oplus R$$P+Q+R$$\overline{P+Q+R}$
go_editor
8.8k
views
go_editor
asked
Sep 29, 2014
Digital Logic
gatecse-2010
digital-logic
circuit-output
easy
+
–
25
votes
4
answers
87
GATE CSE 2011 | Question: 50
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration. If at some instance prior to the occurrence of the clock edge, $P, Q$ and $R$ have a value $0$, $1$ and $0$ respectively, what shall be the value of $PQR$ after the clock edge? $000$ $001$ $010$ $011$
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.If at some instance prior to the occurrence of the clock ...
go_editor
11.1k
views
go_editor
asked
Sep 29, 2014
Digital Logic
gatecse-2011
digital-logic
circuit-output
flip-flop
normal
+
–
27
votes
5
answers
88
GATE CSE 2014 Set 3 | Question: 45
The above synchronous sequential circuit built using JK flip-flops is initialized with $Q_2Q_1Q_0 = 000$. The state sequence for this circuit for the next $3$ clock cycles is $001, 010, 011$ $111, 110, 101$ $100, 110, 111$ $100, 011, 001$
The above synchronous sequential circuit built using JK flip-flops is initialized with $Q_2Q_1Q_0 = 000$. The state sequence for this circuit for the next $3$ clock cycle...
go_editor
17.4k
views
go_editor
asked
Sep 28, 2014
Digital Logic
gatecse-2014-set3
digital-logic
circuit-output
normal
+
–
32
votes
3
answers
89
GATE CSE 1999 | Question: 2.8
Consider the circuit shown below. In a certain steady state, the line $Y$ is at $'1'$. What are the possible values of $A, B$ and $C$ in this state? $A=0, B=0, C=1$ $A=0, B=1, C=1$ $A=1, B=0, C=1$ $A=1, B=1, C=1$
Consider the circuit shown below. In a certain steady state, the line $Y$ is at $'1'$. What are the possible values of $A, B$ and $C$ in this state?$A=0, B=0, C=1$$A=0, B...
Kathleen
7.4k
views
Kathleen
asked
Sep 23, 2014
Digital Logic
gate1999
digital-logic
circuit-output
normal
+
–
26
votes
3
answers
90
GATE CSE 2005 | Question: 64
Consider the following circuit: The flip-flops are positive edge triggered $D$ $\textsf{FF}$s. Each state is designated as a two-bit string $Q_0Q_1$. Let the initial state be $00.$ The state transition sequence is
Consider the following circuit:The flip-flops are positive edge triggered $D$ $\textsf{FF}$s. Each state is designated as a two-bit string $Q_0Q_1$. Let the initial state...
Kathleen
9.3k
views
Kathleen
asked
Sep 22, 2014
Digital Logic
gatecse-2005
digital-logic
circuit-output
+
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