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Recent questions tagged multiplexer
6
6 votes
2
2 answers
239
239 views
GO Classes DPP | GATE CS | Digital Logic | MUX with Enable
A $2:1$ MUX has inputs $\mathrm{I}_0,\mathrm{I}_1$, select line $\mathrm{S}$, and active-low enable input $\mathrm{E}$. When $\mathrm{E}=1$, the output is $0$. When $\mat...
GO Classes
239
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Jun 17
Digital Logic
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3
3 votes
2
2 answers
220
220 views
GO Classes DPP | GATE CS | Digital Logic | Large MUX using Smaller MUX
How many $4:1$ MUXes are required to implement one $16:1$ MUX?$4$ $5$ $6$ $8$
GO Classes
220
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Jun 17
Digital Logic
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11
11 votes
2
2 answers
265
265 views
GO Classes DPP | GATE CS | Digital Logic | MUX Realization
The Boolean function $\mathrm{F}(\mathrm{A},\mathrm{B},\mathrm{C},\mathrm{D})=\Sigma _m(2,3,4,6,9,10,12,13,14,15)$ is to be implemented using a $4:1$ MUX with select line...
GO Classes
265
views
asked
Jun 16
Digital Logic
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digital-logic
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6
6 votes
1
1 answer
169
169 views
GO Classes DPP | GATE CS | Digital Logic | Cascaded MUX
Two $2:1$ MUXes are connected as follows :The first MUX has select line $\mathrm{A}$, input $\mathrm{I}_0=\mathrm{B}$, input $\mathrm{I}_1=\mathrm{C}$, and output $\mathr...
GO Classes
169
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asked
Jun 16
Digital Logic
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4
4 votes
1
1 answer
147
147 views
GO Classes DPP | GATE CS | Digital Logic | MUX Output
A $4:1$ MUX has select lines $\mathrm{S}_1=\mathrm{R}$ and $\mathrm{S}_0=\mathrm{S}$, where $\mathrm{R}$ is MSB and $\mathrm{S}$ is LSB. The data inputs are $\mathrm{I}_0...
GO Classes
147
views
asked
Jun 16
Digital Logic
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5
5 votes
1
1 answer
173
173 views
GO Classes DPP | GATE CS | Digital Logic | MUX
The function $\mathrm{F}(\mathrm{A},\mathrm{B})=\mathrm{A}\oplus\mathrm{B}$ is implemented using an $8:1$ MUX. The select lines are connected as $\mathrm{S}_2=0$, $\mathr...
GO Classes
173
views
asked
Jun 16
Digital Logic
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7
7 votes
2
2 answers
185
185 views
GO Classes DPP | GATE CS | Digital Logic | MUX
The Boolean function $\mathrm{F}(\mathrm{A},\mathrm{B},\mathrm{C})=\Sigma _m(1,2,4,7)$ is to be implemented using a $2:1$ MUX with select line $\mathrm{S}=\mathrm{A}$. Wh...
GO Classes
185
views
asked
Jun 16
Digital Logic
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6
6 votes
2
2 answers
248
248 views
GO Classes DPP | GATE CS | Digital Logic | 8:1 MUX
The function $\mathrm{F}(\mathrm{A},\mathrm{B},\mathrm{C},\mathrm{D})=\Sigma _m(1,2,4,7,8,11,13,14)$ is to be implemented using an $8:1$ MUX with select lines $\mathrm{S}...
GO Classes
248
views
asked
Jun 15
Digital Logic
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3
3 votes
2
2 answers
208
208 views
GO Classes DPP | GATE CS | Digital Logic | MUX Expression
A $4:1$ MUX has select lines $\mathrm{R}$ and $\mathrm{S}$, where $\mathrm{R}$ is the MSB and $\mathrm{S}$ is the LSB. The data inputs are $\mathrm{I}_0=\mathrm{P}+\mathr...
GO Classes
208
views
asked
Jun 15
Digital Logic
goclasses
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multiplexer
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5
5 votes
2
2 answers
175
175 views
GO Classes DPP | GATE CS | Digital Logic | 2:1 MUX
The function $\mathrm{F}(\mathrm{A},\mathrm{B})=\mathrm{A}\oplus\mathrm{B}$ is to be implemented using a $2:1$ MUX with select line $\mathrm{S}=\mathrm{A}$. What should b...
GO Classes
175
views
asked
Jun 15
Digital Logic
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4
4 votes
2
2 answers
178
178 views
GO Classes DPP | GATE CS | Digital Logic | MUX Implementation
The function $\mathrm{F}(\mathrm{A},\mathrm{B},\mathrm{C})=\Sigma _m(1,2,5,7)$ is to be implemented using a $4:1$ MUX with select lines $\mathrm{S}_1=\mathrm{A}$ and $\ma...
GO Classes
178
views
asked
Jun 15
Digital Logic
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digital-logic
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6
6 votes
2
2 answers
227
227 views
GO Classes DPP | GATE CS | Digital Logic | MUX Output
A $4:1$ MUX has select lines $\mathrm{S}_1=\mathrm{A}$ and $\mathrm{S}_0=\mathrm{B}$. The data inputs are $\mathrm{I}_0=0$, $\mathrm{I}_1=\mathrm{C}$, $\mathrm{I}_2=\math...
GO Classes
227
views
asked
Jun 15
Digital Logic
goclasses
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digital-logic
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multiplexer
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1
1 vote
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0 answers
239
239 views
UGC NET CSE | December 2023 | Part 2 | Question: 33
A multiplexes combines for $100$ Kbps channels using a time slot of $2$ bits. What is the bit rate?$100$ Kbps$200$ Kbps$40$ Kbps$1000$ Kbps
Shubham Sharma 2
239
views
asked
Sep 9, 2025
Computer Networks
ugcnetcse-dec2023
computer-networks
multiplexer
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3
3 votes
2
2 answers
406
406 views
GO Classes DPP | Digital logics | Multiplexers
In the circuit shown, $W$ and $Y$ are MSBs of the control inputs. The output $F$ is given by$F=W \bar{X}+\bar{W} X+\bar{Y} \bar{Z}$ $F=W \bar{X}+\bar{W} X+\bar{Y} Z$ $F=W...
GO Classes
406
views
asked
Jun 28, 2025
Programming in C
goclasses
digital-logic
multiplexer
goclasses-cs-dpp
goclasses-cs-dpp-day-30
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1
1 vote
5
5 answers
669
669 views
GO Classes DPP | Digital logics | Combinational circuits | GATE EC
The figure below shows a multiplexer where $S_1$ and $S_0$ are the select lines, $I_5$ to $I_5$ are the input data lines, EN is the enable line, and $P(P, Q, R)$ is the o...
GO Classes
669
views
asked
Jun 24, 2025
Digital Logic
goclasses
digital-logic
combinational-circuit
multiplexer
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3
3 votes
2
2 answers
530
530 views
GO Classes DPP | Digital logic | Multiplexer | GATE EC 2024
The propagation delay of the $2 \times 1 \mathrm{MUX}$ shown in the circuit is 10 ns . Consider the propagation delay of the inverter as 0 ns .If $S$ is set to 1 then the...
GO Classes
530
views
asked
Jun 19, 2025
Digital Logic
goclasses
digital-logic
multiplexer
goclasses-cs-dpp
goclasses-cs-dpp-day-21
goclasses-digital-logic-practice-questions
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3
3 votes
2
2 answers
437
437 views
GO Classes DPP | Digital logic | Multiplexer | Morris Mano
Q. An 8-to-1 multiplexer has its select lines $S_2, S_1, S_0$ connected to $A, B, C$ respectively. The data inputs are as follows:$$\begin{aligned}& I_1=I_2=I_7=0 \\& I_3...
GO Classes
437
views
asked
Jun 19, 2025
Digital Logic
goclasses
digital-logic
multiplexer
goclasses-cs-dpp
goclasses-cs-dpp-day-21
goclasses-digital-logic-practice-questions
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3
3 votes
4
4 answers
845
845 views
GO Classes DPP | Digital Logic | Multiplexer | Philadelphia University
The Boolean function realized by the logic circuit shown is$\quad F=\Sigma m(0,1,3,5,9,10.14)$$\quad \mathrm{F}=\Sigma \mathrm{m}(2,3,5,7,8,12.13)$$\quad F=\Sigma m(1,2,4...
GO Classes
845
views
asked
Jun 8, 2025
Digital Logic
goclasses
digital-logic
multiplexer
goclasses-cs-dpp
goclasses-cs-dpp-day-10
goclasses-digital-logic-practice-questions
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10
10 votes
11
11 answers
1.4k
1.4k views
GO Classes DPP | Digital Logic | Multiplexer Output, Boolean Algebra| Philadelphia University
An 8-to-1 multiplexer has inputs $\mathbf{A}, \mathbf{B}$, and $\mathbf{C}$ connected to the selection inputs $\mathbf{S2}, \mathbf{S1}$, and $\mathbf{S0}$, respectively....
GO Classes
1.4k
views
asked
May 31, 2025
Digital Logic
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digital-logic
multiplexer
boolean-algebra
circuit-output
combinational-circuit
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goclasses-digital-logic-practice-questions
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0
0 votes
1
1 answer
290
290 views
GO Classes Test Series 2025 | NIELIT Mock Test 1 | Question: 66
The propagation delay of the $2 \times 1$ MUX shown in the circuit is $10 \mathrm{~ns}$. Consider the propagation delay of the inverter as $0 \mathrm{~ns}$.If $\text...
GO Classes
290
views
asked
May 5, 2025
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