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Recent questions tagged multiplexer
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Morris Mano Edition 3 Exercise 5 Question 31 (Page No. 200)
specify the size of a ROM ( Number of words and number of bits per words) that will accommodate the truth table for the following combinational circuit components: A binary multiplexer that multiplies two 4bit numbers. A 4 ... to1 line multiplexer with common select and enable inputs. A BCDtosevensegment decoder with an enable input.
asked
Apr 4, 2019
in
Digital Logic
by
ajaysoni1924
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digitallogic
combinationalcircuits
multiplexer
rom
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2
Morris Mano Edition 3 Exercise 5 Question 28 (Page No. 200)
Implement the following boolean function with $4 \times 1$ multiplexer and external gates, connect A and B to selection lines. The input requirement for the four lines will be a function of C and D. These values are obtained by expressing F as a function ... be implemented with the external gates. $F(A,B,C,D) = \sum(1,3,4,11,12,13,14,15)$
asked
Apr 3, 2019
in
Digital Logic
by
ajaysoni1924
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78
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digitallogic
combinationalcircuits
multiplexer
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3
Morris Mano Edition 3 Exercise 5 Question 27 (Page No. 200)
An $8 \times 1$ multiplexer has inputs A,B and C connected to the selection inputs $s _2,s _1$ and $s _0$ respectively.The data inputs $I _0$ through $I _7$ are as follows: $I _1 = I _2 = I _7 = 0$; $ I _3 = I _5 = 1$; $ I _0 = I _4 = D$; and $I _6 = D’$.Determine the boolean function that the multiplexer implements.
asked
Apr 3, 2019
in
Digital Logic
by
ajaysoni1924
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digitallogic
combinationalcircuits
multiplexer
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4
Morris Mano Edition 3 Exercise 5 Question 25 (Page No. 200)
Implement a Full adder with two $4 \times 1$ multiplexers.
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Apr 3, 2019
in
Digital Logic
by
ajaysoni1924
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12
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digitallogic
combinationalcircuits
multiplexer
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5
Morris Mano Edition 3 Exercise 5 Question 23 (Page No. 200)
Construct a $16 \times 1$ multiplexer with two $8 \times 1$ and one $ 2 \times 1$ multiplexers.use the block diagram for the three multiplexers.
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Apr 3, 2019
in
Digital Logic
by
ajaysoni1924
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14
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digitallogic
combinationalcircuits
multiplexer
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6
Morris Mano Edition 3 Exercise 5 Question 22 (Page No. 200)
Draw the logic diagram of a dual 4to1 line multiplexer with common selection inputs and a common enable input.
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Apr 3, 2019
in
Digital Logic
by
ajaysoni1924
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11.1k
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21
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digitallogic
combinationalcircuits
multiplexer
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1
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7
Multiplexer
what is the Minimum number of 21 multiplexers required to realize the following function Assume that inputs are available only in true and Boolean constants 1 and 0 are available. Shouldn't the answer be 1 ??
asked
Mar 10, 2019
in
Digital Logic
by
s_dr_13
(
423
points)

83
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multiplexer
0
votes
2
answers
8
Multiplexer
Consider the given function F(A,B,C,D) = Σm(2,3,5,6,8,9,11,14) then what is the value connected at input I1 in the figure shown below if the select lines are connected to B & D respectively?
asked
Mar 10, 2019
in
Digital Logic
by
s_dr_13
(
423
points)

96
views
multiplexer
digitallogic
0
votes
1
answer
9
Digital logic
plz tell how it take common B’ and B
asked
Jan 10, 2019
in
Digital Logic
by
Rackson
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1.8k
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40
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digitallogic
multiplexer
0
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1
answer
10
DIgital MUX GFG TEST
asked
Jan 7, 2019
in
Digital Logic
by
muthu kumar
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1.7k
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69
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digitallogic
multiplexer
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0
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11
Digital Logic Made Easy
A 2to1 multiplexer having a switching delay of 1 μs is connected as shown in the figure. The output of the multiplexer is tied to its own select input S. The input which gets selected when S = 0 is tied to 1 and the input that gets selected when S= 1 is tied to 0. The output V0 will be 0 1 Pulse train of frequency 0.5 Mhz Pulse train of frequency 1.0 Mhz
asked
Jan 4, 2019
in
Digital Logic
by
Sambhrant Maurya
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(
4k
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190
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multiplexer
digitallogic
combinationalcircuits
0
votes
0
answers
12
MadeEasy WorkBook: Digital Logic  Multiplexer
Why In' is taken as A'B'C'D'?
asked
Dec 29, 2018
in
Digital Logic
by
Jyoti Kumari97
(
193
points)

78
views
digitallogic
multiplexer
madeeasybooklet
0
votes
0
answers
13
MadeEasy WorkBook: Digital Logic  Multiplexer
Can any explain the output function F? According to me F=(Z'C'+Z'C)
asked
Dec 29, 2018
in
Digital Logic
by
Jyoti Kumari97
(
193
points)

75
views
digitallogic
selfdoubt
multiplexer
madeeasybooklet
0
votes
0
answers
14
MadeEasy WorkBook: Digital Logic  Multiplexer
Can anyone explain this.??
asked
Dec 29, 2018
in
Digital Logic
by
Jyoti Kumari97
(
193
points)

65
views
selfdoubt
digitallogic
multiplexer
madeeasybooklet
0
votes
0
answers
15
Digital Logic: GATEECE2016
answer is 6 but I’m getting 5(delay of NOR gate+delay of 1st MUX+delay of 2nd MUX)=2+1.5+1.5=5 ns where is extra 1 ns delay coming from?
asked
Nov 25, 2018
in
Digital Logic
by
aditi19
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5.3k
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195
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usergate20161
digitallogic
multiplexer
0
votes
0
answers
16
digital logic
....
asked
Nov 19, 2018
in
Digital Logic
by
Gurdeep Saini
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10.7k
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71
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digitallogic
digitalcircuits
multiplexer
0
votes
0
answers
17
Gateforum Test Series: Digital Logic  Multiplexer
Can anyone explain briefly i was unable to understand
asked
Nov 16, 2018
in
Digital Logic
by
nag.swarna
(
191
points)

92
views
gateforumtestseries
digitallogic
multiplexer
0
votes
1
answer
18
Gateforum Test Series: Digital Logic  Multiplexer
The answer is given B. Please explain the approach.
asked
Nov 7, 2018
in
Digital Logic
by
Gupta731
Active
(
4.9k
points)

137
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gateforumtestseries
digitallogic
multiplexer
+1
vote
1
answer
19
MadeEasy Full Length Test 2018: Digital Logic  Multiplexer
If A and B are connected to the select lines of the MUX circuit, then the minterms of the boolean function recognized by the circuit are _____ ?
asked
Nov 1, 2018
in
Digital Logic
by
kapilbk1996
(
415
points)

230
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digitallogic
multiplexer
digitalcircuits
booleanalgebra
madeeasytestseries
madeeasytestseries2018
0
votes
0
answers
20
Multiplexer Circuit Output
A 8x1 MUX is used to realize a four variable function, F(A,B,C,D) = Sigma M(0,2,4,6,7,9,14,15). A is LSB which is the input to the MUX. In select lines B is the MSB and D is the LSB THEN input to the MUX From Io to i7 is : A. A' A A' 0 A 0 1 1 B. A A A' 0 A 0 1 1 C. A' A' A 0 A 0 1 1 D. A' A A' 0 A' 0 1 1
asked
Oct 9, 2018
in
Digital Logic
by
Na462
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7.1k
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176
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digitallogic
digitalcircuits
multiplexer
0
votes
1
answer
21
Multiplexer Circuit
The average Propagation of each MUX is 25 ns.The frequency output signal Vo is ?
asked
Oct 9, 2018
in
Digital Logic
by
Na462
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7.1k
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189
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digitallogic
multiplexer
digitalcircuits
0
votes
3
answers
22
Ace Test Series: Digital Logic  Multiplexer
plz explain am not able to solve this .
asked
Sep 3, 2018
in
Digital Logic
by
Shubham Aggarwal
Active
(
1.8k
points)

73
views
acetestseries
digitallogic
multiplexer
+9
votes
2
answers
23
Digital Logic: Gate2016 ECE
The delays of NOR gates, Multiplexer and Inverters are 2ns, 1.5ns and 1ns respectively. If all the inputs P, Q, R, S and T are applied at the same time instant, Then the Maximum propagation delay (in ns) of the circuit is _______________
asked
Aug 12, 2018
in
Digital Logic
by
Magma
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(
14k
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879
views
multiplexer
gate20161
ece
digitallogic
0
votes
2
answers
24
Output of 4 x 1 MUX
What will be the output "Y" of the mux?
asked
Aug 7, 2018
in
Digital Logic
by
Mk Utkarsh
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(
36.9k
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113
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digitallogic
multiplexer
0
votes
1
answer
25
PGEE sample paper
Choose the digital building blocks from the following list using which we can realize any boolean function. (A) 2to1 Multiplexer (B) 4to1 Multiplexer (C) 8to1 Multiplexer (D) 16to1 Multiplexer (E) None of the above
asked
Apr 19, 2018
in
Digital Logic
by
gauravkc
Loyal
(
7.9k
points)

734
views
iiithpgee
booleanalgebra
multiplexer
+1
vote
1
answer
26
Ace Test series: Digital Logic  Multiplexer
asked
Jan 8, 2018
in
Digital Logic
by
Shantanu Ghosh
(
143
points)

237
views
acetestseries
digitallogic
multiplexer
+1
vote
0
answers
27
Ace Test series: Digital Logic  Multiplexer
asked
Jan 4, 2018
in
Digital Logic
by
tonystark007
(
229
points)

121
views
digitallogic
acetestseries
multiplexer
+1
vote
1
answer
28
MadeEasy Test Series: Digital Logic  Multiplexer
please explain how to start solving such circuital questions..I always get confused..plzz help someone asap. What will be the final output?
asked
Dec 29, 2017
in
Digital Logic
by
sunita24
(
403
points)

226
views
madeeasytestseries
digitallogic
decoder
multiplexer
+3
votes
1
answer
29
MadeEasy Test Series: Digital Logic  Multiplexer
A 32 : 1 MUX has to be designed using a 16 : 1 MUX. It was found that for this task we require ‘X ’ number of 16 : 1 MUX and “Y ” number of two input OR gates, then the value of X + Y = __________.
asked
Dec 28, 2017
in
Digital Logic
by
ashish pal
Junior
(
837
points)

453
views
madeeasytestseries
digitallogic
multiplexer
digitalcircuits
0
votes
0
answers
30
Ace Test Series: Digital Logic  Multiplexer
asked
Dec 25, 2017
in
Digital Logic
by
dm4006
Junior
(
561
points)

145
views
acetestseries
digitallogic
multiplexer
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