Login
Register
Dark Mode
Brightness
Ambient Glow – Questions list
Register
Profile
Edit Profile
Messages
My favorites
My Updates
Logout
Recent questions tagged multiplexer
6
6 votes
2
2 answers
288
288 views
GO Classes DPP | GATE CS | Digital Logic | MUX with Enable
A $2:1$ MUX has inputs $\mathrm{I}_0,\mathrm{I}_1$, select line $\mathrm{S}$, and active-low enable input $\mathrm{E}$. When $\mathrm{E}=1$, the output is $0$. When $\mat...
GO Classes
288
views
asked
Jun 17
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-300
goclasses-digital-logic-practice-questions
multiplexer
+
–
3
3 votes
3
3 answers
276
276 views
GO Classes DPP | GATE CS | Digital Logic | Large MUX using Smaller MUX
How many $4:1$ MUXes are required to implement one $16:1$ MUX?$4$ $5$ $6$ $8$
GO Classes
276
views
asked
Jun 17
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-300
goclasses-digital-logic-practice-questions
multiplexer
+
–
11
11 votes
2
2 answers
318
318 views
GO Classes DPP | GATE CS | Digital Logic | MUX Realization
The Boolean function $\mathrm{F}(\mathrm{A},\mathrm{B},\mathrm{C},\mathrm{D})=\Sigma _m(2,3,4,6,9,10,12,13,14,15)$ is to be implemented using a $4:1$ MUX with select line...
GO Classes
318
views
asked
Jun 16
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-299
goclasses-digital-logic-practice-questions
multiplexer
+
–
6
6 votes
1
1 answer
196
196 views
GO Classes DPP | GATE CS | Digital Logic | Cascaded MUX
Two $2:1$ MUXes are connected as follows :The first MUX has select line $\mathrm{A}$, input $\mathrm{I}_0=\mathrm{B}$, input $\mathrm{I}_1=\mathrm{C}$, and output $\mathr...
GO Classes
196
views
asked
Jun 16
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-299
goclasses-digital-logic-practice-questions
multiplexer
+
–
4
4 votes
1
1 answer
175
175 views
GO Classes DPP | GATE CS | Digital Logic | MUX Output
A $4:1$ MUX has select lines $\mathrm{S}_1=\mathrm{R}$ and $\mathrm{S}_0=\mathrm{S}$, where $\mathrm{R}$ is MSB and $\mathrm{S}$ is LSB. The data inputs are $\mathrm{I}_0...
GO Classes
175
views
asked
Jun 16
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-299
goclasses-digital-logic-practice-questions
multiplexer
+
–
5
5 votes
1
1 answer
204
204 views
GO Classes DPP | GATE CS | Digital Logic | MUX
The function $\mathrm{F}(\mathrm{A},\mathrm{B})=\mathrm{A}\oplus\mathrm{B}$ is implemented using an $8:1$ MUX. The select lines are connected as $\mathrm{S}_2=0$, $\mathr...
GO Classes
204
views
asked
Jun 16
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-299
goclasses-digital-logic-practice-questions
multiplexer
+
–
7
7 votes
2
2 answers
223
223 views
GO Classes DPP | GATE CS | Digital Logic | MUX
The Boolean function $\mathrm{F}(\mathrm{A},\mathrm{B},\mathrm{C})=\Sigma _m(1,2,4,7)$ is to be implemented using a $2:1$ MUX with select line $\mathrm{S}=\mathrm{A}$. Wh...
GO Classes
223
views
asked
Jun 16
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-299
goclasses-digital-logic-practice-questions
multiplexer
+
–
6
6 votes
2
2 answers
281
281 views
GO Classes DPP | GATE CS | Digital Logic | 8:1 MUX
The function $\mathrm{F}(\mathrm{A},\mathrm{B},\mathrm{C},\mathrm{D})=\Sigma _m(1,2,4,7,8,11,13,14)$ is to be implemented using an $8:1$ MUX with select lines $\mathrm{S}...
GO Classes
281
views
asked
Jun 15
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-298
goclasses-digital-logic-practice-questions
multiplexer
+
–
3
3 votes
2
2 answers
243
243 views
GO Classes DPP | GATE CS | Digital Logic | MUX Expression
A $4:1$ MUX has select lines $\mathrm{R}$ and $\mathrm{S}$, where $\mathrm{R}$ is the MSB and $\mathrm{S}$ is the LSB. The data inputs are $\mathrm{I}_0=\mathrm{P}+\mathr...
GO Classes
243
views
asked
Jun 15
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-298
goclasses-digital-logic-practice-questions
multiplexer
+
–
5
5 votes
2
2 answers
204
204 views
GO Classes DPP | GATE CS | Digital Logic | 2:1 MUX
The function $\mathrm{F}(\mathrm{A},\mathrm{B})=\mathrm{A}\oplus\mathrm{B}$ is to be implemented using a $2:1$ MUX with select line $\mathrm{S}=\mathrm{A}$. What should b...
GO Classes
204
views
asked
Jun 15
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-298
goclasses-digital-logic-practice-questions
multiplexer
+
–
4
4 votes
2
2 answers
212
212 views
GO Classes DPP | GATE CS | Digital Logic | MUX Implementation
The function $\mathrm{F}(\mathrm{A},\mathrm{B},\mathrm{C})=\Sigma _m(1,2,5,7)$ is to be implemented using a $4:1$ MUX with select lines $\mathrm{S}_1=\mathrm{A}$ and $\ma...
GO Classes
212
views
asked
Jun 15
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-298
goclasses-digital-logic-practice-questions
multiplexer
+
–
6
6 votes
2
2 answers
260
260 views
GO Classes DPP | GATE CS | Digital Logic | MUX Output
A $4:1$ MUX has select lines $\mathrm{S}_1=\mathrm{A}$ and $\mathrm{S}_0=\mathrm{B}$. The data inputs are $\mathrm{I}_0=0$, $\mathrm{I}_1=\mathrm{C}$, $\mathrm{I}_2=\math...
GO Classes
260
views
asked
Jun 15
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-298
goclasses-digital-logic-practice-questions
multiplexer
+
–
1
1 vote
0
0 answers
252
252 views
UGC NET CSE | December 2023 | Part 2 | Question: 33
A multiplexes combines for $100$ Kbps channels using a time slot of $2$ bits. What is the bit rate?$100$ Kbps$200$ Kbps$40$ Kbps$1000$ Kbps
Shubham Sharma 2
252
views
asked
Sep 9, 2025
Computer Networks
ugcnetcse-dec2023
computer-networks
multiplexer
+
–
3
3 votes
2
2 answers
426
426 views
GO Classes DPP | Digital logics | Multiplexers
In the circuit shown, $W$ and $Y$ are MSBs of the control inputs. The output $F$ is given by$F=W \bar{X}+\bar{W} X+\bar{Y} \bar{Z}$ $F=W \bar{X}+\bar{W} X+\bar{Y} Z$ $F=W...
GO Classes
426
views
asked
Jun 28, 2025
Programming in C
goclasses
digital-logic
multiplexer
goclasses-cs-dpp
goclasses-cs-dpp-day-30
goclasses-digital-logic-practice-questions
+
–
1
1 vote
5
5 answers
700
700 views
GO Classes DPP | Digital logics | Combinational circuits | GATE EC
The figure below shows a multiplexer where $S_1$ and $S_0$ are the select lines, $I_5$ to $I_5$ are the input data lines, EN is the enable line, and $P(P, Q, R)$ is the o...
GO Classes
700
views
asked
Jun 24, 2025
Digital Logic
goclasses
digital-logic
combinational-circuit
multiplexer
goclasses-cs-dpp
goclasses-cs-dpp-day-26
goclasses-digital-logic-practice-questions
+
–
3
3 votes
2
2 answers
561
561 views
GO Classes DPP | Digital logic | Multiplexer | GATE EC 2024
The propagation delay of the $2 \times 1 \mathrm{MUX}$ shown in the circuit is 10 ns . Consider the propagation delay of the inverter as 0 ns .If $S$ is set to 1 then the...
GO Classes
561
views
asked
Jun 19, 2025
Digital Logic
goclasses
digital-logic
multiplexer
goclasses-cs-dpp
goclasses-cs-dpp-day-21
goclasses-digital-logic-practice-questions
+
–
3
3 votes
2
2 answers
456
456 views
GO Classes DPP | Digital logic | Multiplexer | Morris Mano
Q. An 8-to-1 multiplexer has its select lines $S_2, S_1, S_0$ connected to $A, B, C$ respectively. The data inputs are as follows:$$\begin{aligned}& I_1=I_2=I_7=0 \\& I_3...
GO Classes
456
views
asked
Jun 19, 2025
Digital Logic
goclasses
digital-logic
multiplexer
goclasses-cs-dpp
goclasses-cs-dpp-day-21
goclasses-digital-logic-practice-questions
+
–
3
3 votes
4
4 answers
871
871 views
GO Classes DPP | Digital Logic | Multiplexer | Philadelphia University
The Boolean function realized by the logic circuit shown is$\quad F=\Sigma m(0,1,3,5,9,10.14)$$\quad \mathrm{F}=\Sigma \mathrm{m}(2,3,5,7,8,12.13)$$\quad F=\Sigma m(1,2,4...
GO Classes
871
views
asked
Jun 8, 2025
Digital Logic
goclasses
digital-logic
multiplexer
goclasses-cs-dpp
goclasses-cs-dpp-day-10
goclasses-digital-logic-practice-questions
+
–
10
10 votes
11
11 answers
1.4k
1.4k views
GO Classes DPP | Digital Logic | Multiplexer Output, Boolean Algebra| Philadelphia University
An 8-to-1 multiplexer has inputs $\mathbf{A}, \mathbf{B}$, and $\mathbf{C}$ connected to the selection inputs $\mathbf{S2}, \mathbf{S1}$, and $\mathbf{S0}$, respectively....
GO Classes
1.4k
views
asked
May 31, 2025
Digital Logic
goclasses
digital-logic
multiplexer
boolean-algebra
circuit-output
combinational-circuit
goclasses-cs-dpp
goclasses-cs-dpp-day-2
goclasses-digital-logic-practice-questions
+
–
0
0 votes
1
1 answer
305
305 views
GO Classes Test Series 2025 | NIELIT Mock Test 1 | Question: 66
The propagation delay of the $2 \times 1$ MUX shown in the circuit is $10 \mathrm{~ns}$. Consider the propagation delay of the inverter as $0 \mathrm{~ns}$.If $\text...
GO Classes
305
views
asked
May 5, 2025
Others
goclasses2025-nielit-mock-1
goclasses
one-mark
digital-logic
sequential-circuit
multiplexer
+
–
Page:
1
2
3
4
5
6
7
next »